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[CostModel][X86] Improve cost estimation of insert_subvector shuffle patterns of legalized types #119363

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Dec 10, 2024
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[CostModel][X86] Improve cost estimation of insert_subvector shuffle patterns of legalized types #119363

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9 changes: 7 additions & 2 deletions llvm/lib/Target/X86/X86TargetTransformInfo.cpp
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Expand Up @@ -1630,14 +1630,19 @@ InstructionCost X86TTIImpl::getShuffleCost(

// Subvector insertions are cheap if the subvectors are aligned.
// Note that in general, the insertion starting at the beginning of a vector
// isn't free, because we need to preserve the rest of the wide vector.
// isn't free, because we need to preserve the rest of the wide vector,
// but if the destination vector legalizes to the same width as the subvector
// then the insertion will simplify to a (free) register copy.
if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) {
int NumElts = LT.second.getVectorNumElements();
std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
if (SubLT.second.isVector()) {
int NumSubElts = SubLT.second.getVectorNumElements();
bool MatchingTypes =
NumElts == NumSubElts &&
(SubTp->getElementCount().getKnownMinValue() % NumSubElts) == 0;
if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
return SubLT.first;
return MatchingTypes ? TTI::TCC_Free : SubLT.first;
}

// If the insertion isn't aligned, treat it like a 2-op shuffle.
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84 changes: 42 additions & 42 deletions llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
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84 changes: 42 additions & 42 deletions llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
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84 changes: 42 additions & 42 deletions llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
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84 changes: 42 additions & 42 deletions llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
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98 changes: 49 additions & 49 deletions llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
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98 changes: 49 additions & 49 deletions llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
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98 changes: 49 additions & 49 deletions llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
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98 changes: 49 additions & 49 deletions llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
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39 changes: 26 additions & 13 deletions llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
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Expand Up @@ -64,11 +64,18 @@ define <16 x i32> @concat_sext_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) {
}

define <8 x i32> @concat_sext_v4i1_v8i32(<4 x i1> %a0, <4 x i1> %a1) {
; CHECK-LABEL: define <8 x i32> @concat_sext_v4i1_v8i32(
; CHECK-SAME: <4 x i1> [[A0:%.*]], <4 x i1> [[A1:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i1> [[A0]], <4 x i1> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[R:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i32>
; CHECK-NEXT: ret <8 x i32> [[R]]
; SSE-LABEL: define <8 x i32> @concat_sext_v4i1_v8i32(
; SSE-SAME: <4 x i1> [[A0:%.*]], <4 x i1> [[A1:%.*]]) #[[ATTR0]] {
; SSE-NEXT: [[X0:%.*]] = sext <4 x i1> [[A0]] to <4 x i32>
; SSE-NEXT: [[X1:%.*]] = sext <4 x i1> [[A1]] to <4 x i32>
; SSE-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[X0]], <4 x i32> [[X1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; SSE-NEXT: ret <8 x i32> [[R]]
;
; AVX-LABEL: define <8 x i32> @concat_sext_v4i1_v8i32(
; AVX-SAME: <4 x i1> [[A0:%.*]], <4 x i1> [[A1:%.*]]) #[[ATTR0]] {
; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x i1> [[A0]], <4 x i1> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; AVX-NEXT: [[R:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i32>
; AVX-NEXT: ret <8 x i32> [[R]]
;
%x0 = sext <4 x i1> %a0 to <4 x i32>
%x1 = sext <4 x i1> %a1 to <4 x i32>
Expand All @@ -90,11 +97,18 @@ define <8 x i16> @concat_trunc_v4i32_v8i16(<4 x i32> %a0, <4 x i32> %a1) {
}

define <8 x ptr> @concat_inttoptr_v4i32_v8iptr(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: define <8 x ptr> @concat_inttoptr_v4i32_v8iptr(
; CHECK-SAME: <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0]], <4 x i32> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[R:%.*]] = inttoptr <8 x i32> [[TMP1]] to <8 x ptr>
; CHECK-NEXT: ret <8 x ptr> [[R]]
; SSE-LABEL: define <8 x ptr> @concat_inttoptr_v4i32_v8iptr(
; SSE-SAME: <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]]) #[[ATTR0]] {
; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0]], <4 x i32> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; SSE-NEXT: [[R:%.*]] = inttoptr <8 x i32> [[TMP1]] to <8 x ptr>
; SSE-NEXT: ret <8 x ptr> [[R]]
;
; AVX-LABEL: define <8 x ptr> @concat_inttoptr_v4i32_v8iptr(
; AVX-SAME: <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]]) #[[ATTR0]] {
; AVX-NEXT: [[X0:%.*]] = inttoptr <4 x i32> [[A0]] to <4 x ptr>
; AVX-NEXT: [[X1:%.*]] = inttoptr <4 x i32> [[A1]] to <4 x ptr>
; AVX-NEXT: [[R:%.*]] = shufflevector <4 x ptr> [[X0]], <4 x ptr> [[X1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; AVX-NEXT: ret <8 x ptr> [[R]]
;
%x0 = inttoptr <4 x i32> %a0 to <4 x ptr>
%x1 = inttoptr <4 x i32> %a1 to <4 x ptr>
Expand Down Expand Up @@ -138,9 +152,8 @@ define <8 x double> @concat_fpext_v4f32_v8f64(<4 x float> %a0, <4 x float> %a1)
define <16 x float> @concat_fptrunc_v8f64_v16f32(<8 x double> %a0, <8 x double> %a1) {
; CHECK-LABEL: define <16 x float> @concat_fptrunc_v8f64_v16f32(
; CHECK-SAME: <8 x double> [[A0:%.*]], <8 x double> [[A1:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[X0:%.*]] = fptrunc <8 x double> [[A0]] to <8 x float>
; CHECK-NEXT: [[X1:%.*]] = fptrunc <8 x double> [[A1]] to <8 x float>
; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x float> [[X0]], <8 x float> [[X1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x double> [[A0]], <8 x double> [[A1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[R:%.*]] = fptrunc <16 x double> [[TMP1]] to <16 x float>
; CHECK-NEXT: ret <16 x float> [[R]]
;
%x0 = fptrunc <8 x double> %a0 to <8 x float>
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19 changes: 6 additions & 13 deletions llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
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Expand Up @@ -34,19 +34,12 @@ entry:
}

define <8 x i32> @test3(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3) {
; SSE-LABEL: @test3(
; SSE-NEXT: entry:
; SSE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP1:%.*]])
; SSE-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP2:%.*]], <4 x i32> [[TMP3:%.*]])
; SSE-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; SSE-NEXT: ret <8 x i32> [[TMP6]]
;
; AVX-LABEL: @test3(
; AVX-NEXT: entry:
; AVX-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; AVX-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1:%.*]], <4 x i32> [[TMP3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; AVX-NEXT: [[TMP6:%.*]] = call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
; AVX-NEXT: ret <8 x i32> [[TMP6]]
; CHECK-LABEL: @test3(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1:%.*]], <4 x i32> [[TMP3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
; CHECK-NEXT: ret <8 x i32> [[TMP6]]
;
entry:
%4 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1)
Expand Down
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