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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (3/11) #116829

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Dec 2, 2024
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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (3/11) #116829

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c4760fc
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (3/11)
momchil-velikov Nov 19, 2024
9b0d3b2
[fixup] Add some missing "double %z0" to tests (NFC)
momchil-velikov Dec 2, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4271,10 +4271,10 @@ let Predicates = [HasSVE2p2orSME2p2] in {
defm FCVTNT_ZPzZ : sve_fp_fcvtntz<"fcvtnt">;
def FCVTXNT_ZPzZ_DtoS : sve_fp_fcvt2z<0b0010, "fcvtxnt", ZPR32, ZPR64>;
// Placing even
def FCVTX_ZPzZ_DtoS : sve_fp_z2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32>;
defm FCVTX_ZPzZ : sve_fp_z2op_p_zd<"fcvtx", int_aarch64_sve_fcvtx_f32f64>;

// SVE2p2 floating-point convert precision up, zeroing predicate
defm FCVTLT_ZPzZ : sve_fp_fcvtltz<"fcvtlt">;
defm FCVTLT_ZPzZ : sve_fp_fcvtltz<"fcvtlt", "int_aarch64_sve_fcvtlt">;

// SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
Expand Down
11 changes: 10 additions & 1 deletion llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -2858,9 +2858,12 @@ multiclass sve_fp_fcvtntz<string asm> {
def _DtoS : sve_fp_fcvt2z<0b1110, asm, ZPR32, ZPR64>;
}

multiclass sve_fp_fcvtltz<string asm> {
multiclass sve_fp_fcvtltz<string asm, string op> {
def _HtoS : sve_fp_fcvt2z<0b1001, asm, ZPR32, ZPR16>;
def _StoD : sve_fp_fcvt2z<0b1111, asm, ZPR64, ZPR32>;

def : SVE_3_Op_UndefZero_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f16), nxv4f32, nxv4i1, nxv8f16, !cast<Instruction>(NAME # _HtoS)>;
def : SVE_3_Op_UndefZero_Pat<nxv2f64, !cast<SDPatternOperator>(op # _f64f32), nxv2f64, nxv2i1, nxv4f32, !cast<Instruction>(NAME # _StoD)>;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -3267,6 +3270,12 @@ class sve_fp_z2op_p_zd<bits<7> opc,string asm, RegisterOperand i_zprtype,
let mayRaiseFPException = 1;
}

multiclass sve_fp_z2op_p_zd<string asm, SDPatternOperator op> {
def _DtoS : sve_fp_z2op_p_zd<0b0001010, asm, ZPR64, ZPR32>;

def : SVE_3_Op_UndefZero_Pat<nxv4f32, op, nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
}

multiclass sve_fp_z2op_p_zd_hsd<bits<5> opc, string asm> {
def _H : sve_fp_z2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16>;
def _S : sve_fp_z2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32>;
Expand Down
146 changes: 146 additions & 0 deletions llvm/test/CodeGen/AArch64/zeroing-forms-fcvtlt-fcvtx.ll
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@@ -0,0 +1,146 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2

; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2

target triple = "aarch64-linux"

define <vscale x 4 x float> @test_svcvtlt_f32_f16_x_1(<vscale x 4 x i1> %pg, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svcvtlt_f32_f16_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtlt z0.s, p0/m, z0.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z0.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> undef, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 4 x float> %0
}

define <vscale x 4 x float> @test_svcvtlt_f32_f16_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svcvtlt_f32_f16_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtlt z0.s, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> undef, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 4 x float> %0
}

define <vscale x 4 x float> @test_svcvtlt_f32_f16_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
; CHECK-LABEL: test_svcvtlt_f32_f16_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: fcvtlt z0.s, p0/m, z1.h
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z1.h
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)
ret <vscale x 4 x float> %0
}

define <vscale x 2 x double> @test_svcvtlt_f64_f32_x_1(<vscale x 2 x i1> %pg, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svcvtlt_f64_f32_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtlt z0.d, p0/m, z0.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z0.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> undef, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 2 x double> %0
}

define <vscale x 2 x double> @test_svcvtlt_f64_f32_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svcvtlt_f64_f32_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtlt z0.d, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> undef, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 2 x double> %0
}

define <vscale x 2 x double> @test_svcvtlt_f64_f32_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
; CHECK-LABEL: test_svcvtlt_f64_f32_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.d, #0 // =0x0
; CHECK-NEXT: fcvtlt z0.d, p0/m, z1.s
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z1.s
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)
ret <vscale x 2 x double> %0
}

define <vscale x 4 x float> @test_svcvtx_f32_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svcvtx_f32_f64_x_1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtx z0.s, p0/m, z0.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtx_f32_f64_x_1:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z0.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 4 x float> %0
}

define <vscale x 4 x float> @test_svcvtx_f32_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svcvtx_f32_f64_x_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtx z0.s, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtx_f32_f64_x_2:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 4 x float> %0
}

define <vscale x 4 x float> @test_svcvtx_f32_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
; CHECK-LABEL: test_svcvtx_f32_f64_z:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: fcvtx z0.s, p0/m, z1.d
; CHECK-NEXT: ret
;
; CHECK-2p2-LABEL: test_svcvtx_f32_f64_z:
; CHECK-2p2: // %bb.0: // %entry
; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z1.d
; CHECK-2p2-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
ret <vscale x 4 x float> %0
}