[AArch64]Add convert and multiply-add SIMD&FP assembly/disassembly in… #113296
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-aarch64 Author: None (CarolineConcatto) Changes…structions This patch adds the following instructions: According to https://developer.arm.com/documentation/ddi0602 Co-authored-by: Marian Lukac marian.lukac@arm.com Patch is 37.80 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113296.diff 12 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 4b24b166143dca..740a8fc175fc78 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -5005,6 +5005,32 @@ multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
}
}
+multiclass FPToIntegerSIMDScalar<bits<2> rmode, bits<3> opcode, string asm> {
+ // double-precision to 32-bit SIMD/FPR
+ def SDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, FPR32, asm,
+ []> {
+ let Inst{31} = 0; // 32-bit GPR flag
+ }
+
+ // half-precision to 32-bit SIMD/FPR
+ def SHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, FPR32, asm,
+ []> {
+ let Inst{31} = 0; // 32-bit GPR flag
+ }
+
+ // half-precision to 64-bit SIMD/FPR
+ def DHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, FPR64, asm,
+ []> {
+ let Inst{31} = 1; // 32-bit GPR flag
+ }
+
+ // single-precision to 64-bit SIMD/FPR
+ def DSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, FPR64, asm,
+ []> {
+ let Inst{31} = 1; // 32-bit GPR flag
+ }
+}
+
multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
SDPatternOperator OpN> {
// Scaled half-precision to 32-bit
@@ -5066,7 +5092,7 @@ multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
//---
let mayStore = 0, mayLoad = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
-class BaseIntegerToFP<bit isUnsigned,
+class BaseIntegerToFP<bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType,
Operand immType, string asm, list<dag> pattern>
: I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
@@ -5076,15 +5102,16 @@ class BaseIntegerToFP<bit isUnsigned,
bits<5> Rn;
bits<6> scale;
let Inst{30-24} = 0b0011110;
- let Inst{21-17} = 0b00001;
- let Inst{16} = isUnsigned;
+ let Inst{21} = 0b0;
+ let Inst{20-19} = rmode;
+ let Inst{18-16} = opcode;
let Inst{15-10} = scale;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}
let mayRaiseFPException = 1, Uses = [FPCR] in
-class BaseIntegerToFPUnscaled<bit isUnsigned,
+class BaseIntegerToFPUnscaled<bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType,
ValueType dvt, string asm, SDPatternOperator node>
: I<(outs dstType:$Rd), (ins srcType:$Rn),
@@ -5094,49 +5121,50 @@ class BaseIntegerToFPUnscaled<bit isUnsigned,
bits<5> Rn;
bits<6> scale;
let Inst{30-24} = 0b0011110;
- let Inst{21-17} = 0b10001;
- let Inst{16} = isUnsigned;
+ let Inst{21} = 0b1;
+ let Inst{20-19} = rmode;
+ let Inst{18-16} = opcode;
let Inst{15-10} = 0b000000;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}
-multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
+multiclass IntegerToFP<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator node> {
// Unscaled
- def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
+ def UWHri: BaseIntegerToFPUnscaled<rmode, opcode, GPR32, FPR16, f16, asm, node> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{23-22} = 0b11; // 16-bit FPR flag
let Predicates = [HasFullFP16];
}
- def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
+ def UWSri: BaseIntegerToFPUnscaled<rmode, opcode, GPR32, FPR32, f32, asm, node> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
- def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
+ def UWDri: BaseIntegerToFPUnscaled<rmode, opcode, GPR32, FPR64, f64, asm, node> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{23-22} = 0b01; // 64-bit FPR flag
}
- def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
+ def UXHri: BaseIntegerToFPUnscaled<rmode, opcode, GPR64, FPR16, f16, asm, node> {
let Inst{31} = 1; // 64-bit GPR flag
let Inst{23-22} = 0b11; // 16-bit FPR flag
let Predicates = [HasFullFP16];
}
- def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
+ def UXSri: BaseIntegerToFPUnscaled<rmode, opcode, GPR64, FPR32, f32, asm, node> {
let Inst{31} = 1; // 64-bit GPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
- def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
+ def UXDri: BaseIntegerToFPUnscaled<rmode, opcode, GPR64, FPR64, f64, asm, node> {
let Inst{31} = 1; // 64-bit GPR flag
let Inst{23-22} = 0b01; // 64-bit FPR flag
}
// Scaled
- def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_recip_f16_i32, asm,
+ def SWHri: BaseIntegerToFP<rmode, opcode, GPR32, FPR16, fixedpoint_recip_f16_i32, asm,
[(set (f16 FPR16:$Rd),
(fmul (node GPR32:$Rn),
fixedpoint_recip_f16_i32:$scale))]> {
@@ -5146,7 +5174,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let Predicates = [HasFullFP16];
}
- def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_recip_f32_i32, asm,
+ def SWSri: BaseIntegerToFP<rmode, opcode, GPR32, FPR32, fixedpoint_recip_f32_i32, asm,
[(set FPR32:$Rd,
(fmul (node GPR32:$Rn),
fixedpoint_recip_f32_i32:$scale))]> {
@@ -5155,7 +5183,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let scale{5} = 1;
}
- def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_recip_f64_i32, asm,
+ def SWDri: BaseIntegerToFP<rmode, opcode, GPR32, FPR64, fixedpoint_recip_f64_i32, asm,
[(set FPR64:$Rd,
(fmul (node GPR32:$Rn),
fixedpoint_recip_f64_i32:$scale))]> {
@@ -5164,7 +5192,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let scale{5} = 1;
}
- def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_recip_f16_i64, asm,
+ def SXHri: BaseIntegerToFP<rmode, opcode, GPR64, FPR16, fixedpoint_recip_f16_i64, asm,
[(set (f16 FPR16:$Rd),
(fmul (node GPR64:$Rn),
fixedpoint_recip_f16_i64:$scale))]> {
@@ -5173,7 +5201,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let Predicates = [HasFullFP16];
}
- def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_recip_f32_i64, asm,
+ def SXSri: BaseIntegerToFP<rmode, opcode, GPR64, FPR32, fixedpoint_recip_f32_i64, asm,
[(set FPR32:$Rd,
(fmul (node GPR64:$Rn),
fixedpoint_recip_f32_i64:$scale))]> {
@@ -5181,7 +5209,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
- def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_recip_f64_i64, asm,
+ def SXDri: BaseIntegerToFP<rmode, opcode, GPR64, FPR64, fixedpoint_recip_f64_i64, asm,
[(set FPR64:$Rd,
(fmul (node GPR64:$Rn),
fixedpoint_recip_f64_i64:$scale))]> {
@@ -5190,6 +5218,32 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
}
}
+multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator node = null_frag> {
+ // 32-bit to half-precision
+ def HSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR16, f16, asm, node> {
+ let Inst{31} = 0; // 32-bit GPR flag
+ let Inst{23-22} = 0b11; // 16-bit FPR flag
+ }
+
+ // 32-bit to double-precision
+ def DSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR64, f64, asm, node> {
+ let Inst{31} = 0; // 32-bit GPR flag
+ let Inst{23-22} = 0b01; // 16-bit FPR flag
+ }
+
+ // 64-bit to half-precision
+ def HDr: BaseIntegerToFPUnscaled<rmode, opcode, FPR64, FPR16, f16, asm, node> {
+ let Inst{31} = 1; // 32-bit GPR flag
+ let Inst{23-22} = 0b11; // 16-bit FPR flag
+ }
+
+ // 64-bit to single-precision
+ def SDr: BaseIntegerToFPUnscaled<rmode, opcode, FPR64, FPR32, f32, asm, node> {
+ let Inst{31} = 1; // 32-bit GPR flag
+ let Inst{23-22} = 0b00; // 16-bit FPR flag
+ }
+}
+
//---
// Unscaled integer <-> floating point conversion (i.e. FMOV)
//---
@@ -12687,3 +12741,19 @@ multiclass AtomicFPStore<bit R, bits<3> op0, string asm> {
def S : BaseAtomicFPStore<FPR32, 0b10, R, op0, asm>;
def H : BaseAtomicFPStore<FPR16, 0b01, R, op0, asm>;
}
+
+class BaseSIMDThreeSameVectorFP8MatrixMul<string asm, bits<2> size, string kind>
+ : BaseSIMDThreeSameVectorTied<1, 1, {size, 0}, 0b11101,
+ V128, asm, ".16b", []> {
+ let AsmString = !strconcat(asm, "{\t$Rd", kind, ", $Rn", ".16b",
+ ", $Rm", ".16b", "}");
+}
+
+multiclass SIMDThreeSameVectorFP8MatrixMul<string asm>{
+ def v8f16: BaseSIMDThreeSameVectorFP8MatrixMul<asm, 0b00, ".8h">{
+ let Predicates = [HasNEON, HasF8F16MM];
+ }
+ def v4f32: BaseSIMDThreeSameVectorFP8MatrixMul<asm, 0b10, ".4s">{
+ let Predicates = [HasNEON, HasF8F32MM];
+ }
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 4bd36e9eacbc68..67ce6733da36dc 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4710,6 +4710,19 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
+let Predicates = [HasNEON, HasFPRCVT] in{
+ defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas">;
+ defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau">;
+ defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms">;
+ defm FCVTMU : FPToIntegerSIMDScalar<0b10, 0b101, "fcvtmu">;
+ defm FCVTNS : FPToIntegerSIMDScalar<0b01, 0b010, "fcvtns">;
+ defm FCVTNU : FPToIntegerSIMDScalar<0b01, 0b011, "fcvtnu">;
+ defm FCVTPS : FPToIntegerSIMDScalar<0b10, 0b010, "fcvtps">;
+ defm FCVTPU : FPToIntegerSIMDScalar<0b10, 0b011, "fcvtpu">;
+ defm FCVTZS : FPToIntegerSIMDScalar<0b10, 0b110, "fcvtzs">;
+ defm FCVTZU : FPToIntegerSIMDScalar<0b10, 0b111, "fcvtzu">;
+}
+
// AArch64's FCVT instructions saturate when out of range.
multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {
let Predicates = [HasFullFP16] in {
@@ -4868,8 +4881,13 @@ def : Pat<(i64 (any_llround f64:$Rn)),
// Scaled integer to floating point conversion instructions.
//===----------------------------------------------------------------------===//
-defm SCVTF : IntegerToFP<0, "scvtf", any_sint_to_fp>;
-defm UCVTF : IntegerToFP<1, "ucvtf", any_uint_to_fp>;
+defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>;
+defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>;
+
+let Predicates = [HasNEON, HasFPRCVT] in {
+ defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf">;
+ defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf">;
+}
def : Pat<(f16 (fdiv (f16 (any_sint_to_fp (i32 GPR32:$Rn))), fixedpoint_f16_i32:$scale)),
(SCVTFSWHri GPR32:$Rn, fixedpoint_f16_i32:$scale)>;
@@ -10371,6 +10389,9 @@ let Predicates = [HasLSFE] in {
def STBFMINNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b111, "stbfminnml">;
}
+let Uses = [FPMR, FPCR] in
+defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla">;
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
diff --git a/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s b/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
new file mode 100644
index 00000000000000..cf8d216581240a
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
@@ -0,0 +1,46 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+f8f16mm,+f8f32mm 2>&1 < %s| FileCheck %s
+
+fmmla v0.4h, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.4h, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.8s, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
+// CHECK-NEXT: fmmla v0.8s, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.4s, v1.4s, v2.4s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.4s, v1.4s, v2.4s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.8h, v1.8h, v2.8h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.8h, v1.8h, v2.8h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.16b, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.16b, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.d, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.d, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.2d, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.2d, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.8h, v1.8b, v2.8b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.8h, v1.8b, v2.8b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.4s, v1.8b, v2.8b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.4s, v1.8b, v2.8b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/FP8/fmmla.s b/llvm/test/MC/AArch64/FP8/fmmla.s
new file mode 100644
index 00000000000000..922f4c9d918ce9
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/fmmla.s
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | llvm-objdump -d --mattr=+f8f16mm,+f8f32mm - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=-f8f16mm,-f8f32mm - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+f8f16mm,+f8f32mm -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+fmmla v0.8h, v1.16b, v2.16b
+// CHECK-INST: fmmla v0.8h, v1.16b, v2.16b
+// CHECK-ENCODING: [0x20,0xec,0x02,0x6e]
+// CHECK-ERROR: instruction requires: f8f16mm
+// CHECK-UNKNOWN: 6e02ec20 <unknown>
+
+fmmla v0.4s, v1.16b, v2.16b
+// CHECK-INST: fmmla v0.4s, v1.16b, v2.16b
+// CHECK-ENCODING: [0x20,0xec,0x82,0x6e]
+// CHECK-ERROR: instruction requires: f8f32mm
+// CHECK-UNKNOWN: 6e82ec20 <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/armv9.6a-cvtf.s b/llvm/test/MC/AArch64/armv9.6a-cvtf.s
new file mode 100644
index 00000000000000..6858d3896af5ab
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-cvtf.s
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --mattr=+fprcvt - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=-fprcvt - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+fprcvt -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+scvtf d1, s2
+// CHECK-INST: scvtf d1, s2
+// CHECK-ENCODING: [0x41,0x00,0x7c,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7c0041 <unknown>
+
+scvtf h1, s2
+// CHECK-INST: scvtf h1, s2
+// CHECK-ENCODING: [0x41,0x00,0xfc,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efc0041 <unknown>
+
+scvtf h2, d0
+// CHECK-INST: scvtf h2, d0
+// CHECK-ENCODING: [0x02,0x00,0xfc,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efc0002 <unknown>
+
+scvtf s3, d4
+// CHECK-INST: scvtf s3, d4
+// CHECK-ENCODING: [0x83,0x00,0x3c,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3c0083 <unknown>
+
+ucvtf d1, s2
+// CHECK-INST: ucvtf d1, s2
+// CHECK-ENCODING: [0x41,0x00,0x7d,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7d0041 <unknown>
+
+ucvtf h1, s2
+// CHECK-INST: ucvtf h1, s2
+// CHECK-ENCODING: [0x41,0x00,0xfd,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efd0041 <unknown>
+
+ucvtf h2, d0
+// CHECK-INST: ucvtf h2, d0
+// CHECK-ENCODING: [0x02,0x00,0xfd,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efd0002 <unknown>
+
+ucvtf s3, d4
+// CHECK-INST: ucvtf s3, d4
+// CHECK-ENCODING: [0x83,0x00,0x3d,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3d0083 <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/armv9.6a-fcvt.s b/llvm/test/MC/AArch64/armv9.6a-fcvt.s
new file mode 100644
index 00000000000000..b14ec93563f5c4
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-fcvt.s
@@ -0,0 +1,253 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --mattr=+fprcvt - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=-fprcvt - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+fprcvt -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+fcvtas s0, d1
+// CHECK-INST: fcvtas s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x7a,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7a0020 <unknown>
+
+fcvtas s1, h2
+// CHECK-INST: fcvtas s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xfa,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efa0041 <unknown>
+
+fcvtas d3, h4
+// CHECK-INST: fcvtas d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xfa,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efa0083 <unknown>
+
+fcvtas d0, s5
+// CHECK-INST: fcvtas d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x3a,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3a00a0 <unknown>
+
+fcvtau s0, d1
+// ...
[truncated]
|
jthackray
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jthackray
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…structions
This patch adds the following instructions:
Conversion between floating-point and integer:
FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU}
{S,U}CVTF
Advanced SIMD three-register extension:
FMMLA
According to https://developer.arm.com/documentation/ddi0602
Co-authored-by: Marian Lukac marian.lukac@arm.com
Co-authored-by: Spencer Abson spencer.abson@arm.com
CarolineConcatto
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NoumanAmir657
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Nov 4, 2024
llvm#113296) …structions This patch adds the following instructions: Conversion between floating-point and integer: FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} {S,U}CVTF Advanced SIMD three-register extension: FMMLA According to https://developer.arm.com/documentation/ddi0602 Co-authored-by: Marian Lukac marian.lukac@arm.com Co-authored-by: Spencer Abson spencer.abson@arm.com
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…structions
This patch adds the following instructions:
Conversion between floating-point and integer:
FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU}
{S,U}CVTF
Advanced SIMD three-register extension:
FMMLA
According to https://developer.arm.com/documentation/ddi0602
Co-authored-by: Marian Lukac marian.lukac@arm.com
Co-authored-by: Spencer Abson spencer.abson@arm.com