This patch does 3 things:
1. Add support for optimizing the address mode of HVX load/store
   instructions
2. Reduce the value of Add instruction immediates by replacing with the
   difference from other Addi instructions that share common base:

   For Example, If we have the below sequence of instructions:
       r1 = add(r2,llvm#1024)
            ...
       r3 = add(r2,llvm#1152)
            ...
       r4 = add(r2,llvm#1280)

   Where the register r2 has the same reaching definition, They get modified to
   the below sequence:

       r1 = add(r2,llvm#1024)
            ...
       r3 = add(r1,llvm#128)
            ...
       r4 = add(r1,llvm#256)
3. Fixes a bug pass where the addi instructions were modified based on a
predicated register definition, leading to incorrect output.

Eg:
         INST-1: if (p0) r2 = add(r13,llvm#128)
         INST-2: r1 = add(r2,llvm#1024)
         INST-3: r3 = add(r2,llvm#1152)
         INST-4: r5 = add(r2,llvm#1280)

In the above case, since r2's definition is predicated, we do not want
to modify the uses of r2 in INST-3/INST-4 with add(r1,llvm#128/256)

4.Fixes a corner case

It looks like we never check whether the offset register is actually live (not clobbered)
at optimization site. Add the check whether it is live at MBB entrance.
The rest should have already been verified.

5. Fixes a bad codegen

For whatever reason we do transformation without checking if the value in register actually reaches the user.
This is second identical fix for this pass.

   Co-authored-by: Anirudh Sundar <quic_sanirudh@quicinc.com>
   Co-authored-by: Sergei Larin <slarin@quicinc.com>