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Sep 2, 2024
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AMDGPU/NewPM Port SILoadStoreOptimizer to NPM #106362

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AMDGPU/NewPM Port SILoadStoreOptimizer to NPM
optimisan Aug 28, 2024
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optimisan Aug 29, 2024
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Move MFPropsModifier before optnone skip
optimisan Aug 29, 2024
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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPU.h
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ FunctionPass *createSIPeepholeSDWAPass();
FunctionPass *createSILowerI1CopiesLegacyPass();
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
FunctionPass *createSIShrinkInstructionsPass();
FunctionPass *createSILoadStoreOptimizerPass();
FunctionPass *createSILoadStoreOptimizerLegacyPass();
FunctionPass *createSIWholeQuadModePass();
FunctionPass *createSIFixControlFlowLiveIntervalsPass();
FunctionPass *createSIOptimizeExecMaskingPreRAPass();
Expand Down Expand Up @@ -190,8 +190,8 @@ extern char &AMDGPUMarkLastScratchLoadID;
void initializeSILowerSGPRSpillsPass(PassRegistry &);
extern char &SILowerSGPRSpillsID;

void initializeSILoadStoreOptimizerPass(PassRegistry &);
extern char &SILoadStoreOptimizerID;
void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
extern char &SILoadStoreOptimizerLegacyID;

void initializeSIWholeQuadModePass(PassRegistry &);
extern char &SIWholeQuadModeID;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
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Expand Up @@ -99,4 +99,5 @@ MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
#undef MACHINE_FUNCTION_PASS
5 changes: 3 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Expand Up @@ -36,6 +36,7 @@
#include "R600TargetMachine.h"
#include "SIFixSGPRCopies.h"
#include "SIFoldOperands.h"
#include "SILoadStoreOptimizer.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
Expand Down Expand Up @@ -417,7 +418,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSIShrinkInstructionsPass(*PR);
initializeSIOptimizeExecMaskingPreRAPass(*PR);
initializeSIOptimizeVGPRLiveRangePass(*PR);
initializeSILoadStoreOptimizerPass(*PR);
initializeSILoadStoreOptimizerLegacyPass(*PR);
initializeAMDGPUCtorDtorLoweringLegacyPass(*PR);
initializeAMDGPUAlwaysInlinePass(*PR);
initializeAMDGPUSwLowerLDSLegacyPass(*PR);
Expand Down Expand Up @@ -1275,7 +1276,7 @@ void GCNPassConfig::addMachineSSAOptimization() {
addPass(&SIFoldOperandsLegacyID);
if (EnableDPPCombine)
addPass(&GCNDPPCombineLegacyID);
addPass(&SILoadStoreOptimizerID);
addPass(&SILoadStoreOptimizerLegacyID);
if (isPassEnabled(EnableSDWAPeephole)) {
addPass(&SIPeepholeSDWAID);
addPass(&EarlyMachineLICMID);
Expand Down
64 changes: 47 additions & 17 deletions llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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Expand Up @@ -57,6 +57,7 @@
//
//===----------------------------------------------------------------------===//

#include "SILoadStoreOptimizer.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
Expand Down Expand Up @@ -104,7 +105,7 @@ struct AddressRegs {
// GFX10 image_sample instructions can have 12 vaddrs + srsrc + ssamp.
const unsigned MaxAddressRegs = 12 + 1 + 1;

class SILoadStoreOptimizer : public MachineFunctionPass {
class SILoadStoreOptimizer {
struct CombineInfo {
MachineBasicBlock::iterator I;
unsigned EltSize;
Expand Down Expand Up @@ -295,17 +296,21 @@ class SILoadStoreOptimizer : public MachineFunctionPass {
static InstClassEnum getCommonInstClass(const CombineInfo &CI,
const CombineInfo &Paired);

public:
static char ID;

SILoadStoreOptimizer() : MachineFunctionPass(ID) {
initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
}

bool optimizeInstsWithSameBaseAddr(std::list<CombineInfo> &MergeList,
bool &OptimizeListAgain);
bool optimizeBlock(std::list<std::list<CombineInfo> > &MergeableInsts);

public:
SILoadStoreOptimizer(AliasAnalysis *AA) : AA(AA) {}
bool run(MachineFunction &MF);
};

class SILoadStoreOptimizerLegacy : public MachineFunctionPass {
public:
static char ID;

SILoadStoreOptimizerLegacy() : MachineFunctionPass(ID) {}

bool runOnMachineFunction(MachineFunction &MF) override;

StringRef getPassName() const override { return "SI Load Store Optimizer"; }
Expand Down Expand Up @@ -882,18 +887,18 @@ void SILoadStoreOptimizer::CombineInfo::setMI(MachineBasicBlock::iterator MI,

} // end anonymous namespace.

INITIALIZE_PASS_BEGIN(SILoadStoreOptimizer, DEBUG_TYPE,
INITIALIZE_PASS_BEGIN(SILoadStoreOptimizerLegacy, DEBUG_TYPE,
"SI Load Store Optimizer", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(SILoadStoreOptimizer, DEBUG_TYPE, "SI Load Store Optimizer",
false, false)
INITIALIZE_PASS_END(SILoadStoreOptimizerLegacy, DEBUG_TYPE,
"SI Load Store Optimizer", false, false)

char SILoadStoreOptimizer::ID = 0;
char SILoadStoreOptimizerLegacy::ID = 0;

char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
char &llvm::SILoadStoreOptimizerLegacyID = SILoadStoreOptimizerLegacy::ID;

FunctionPass *llvm::createSILoadStoreOptimizerPass() {
return new SILoadStoreOptimizer();
FunctionPass *llvm::createSILoadStoreOptimizerLegacyPass() {
return new SILoadStoreOptimizerLegacy();
}

static void addDefsUsesToList(const MachineInstr &MI,
Expand Down Expand Up @@ -2522,10 +2527,15 @@ SILoadStoreOptimizer::optimizeInstsWithSameBaseAddr(
return Modified;
}

bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
bool SILoadStoreOptimizerLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
return SILoadStoreOptimizer(
&getAnalysis<AAResultsWrapperPass>().getAAResults())
.run(MF);
}

bool SILoadStoreOptimizer::run(MachineFunction &MF) {
STM = &MF.getSubtarget<GCNSubtarget>();
if (!STM->loadStoreOptEnabled())
return false;
Expand All @@ -2534,7 +2544,6 @@ bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
TRI = &TII->getRegisterInfo();

MRI = &MF.getRegInfo();
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();

LLVM_DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");

Expand Down Expand Up @@ -2571,3 +2580,24 @@ bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {

return Modified;
}

PreservedAnalyses
SILoadStoreOptimizerPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
MFPropsModifier _(*this, MF);

if (MF.getFunction().hasOptNone())
return PreservedAnalyses::all();

auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
.getManager();
AAResults &AA = FAM.getResult<AAManager>(MF.getFunction());

bool Changed = SILoadStoreOptimizer(&AA).run(MF);
if (!Changed)
return PreservedAnalyses::all();

PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
return PA;
}
30 changes: 30 additions & 0 deletions llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h
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@@ -0,0 +1,30 @@
//===--- SILoadStoreOptimizer.h -------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AMDGPU_SILOADSTOREOPTIMIZER_H
#define LLVM_LIB_TARGET_AMDGPU_SILOADSTOREOPTIMIZER_H

#include "llvm/CodeGen/MachinePassManager.h"

namespace llvm {

class SILoadStoreOptimizerPass
: public PassInfoMixin<SILoadStoreOptimizerPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);

MachineFunctionProperties getRequiredProperties() {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::IsSSA);
}
};

} // namespace llvm

#endif // LLVM_LIB_TARGET_AMDGPU_SILOADSTOREOPTIMIZER_H
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
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@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s
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Verify is default when using new pass manager.

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I think the default should be pre and post verify the MIR, and the flag should be interpreted as run after each pass

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@paperchalice I wonder why the verify is default when using NPM? Shouldn't the behavior be consistent with the legacy PM, at least this early stage?

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Because verify is no longer a part in pass pipeline when using new pass manager. New pass manager introduces PassInstrumentation, verify now is now part of StandardInstrumentations::Verify which support both kinds of IRs. This can be disabled by option --disable-verify, but the doc string is not updated...

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we should match opt's -disable-verify and -verify-each

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we should match opt's -disable-verify and -verify-each

Now in #106665.


# The purpose of this test is to make sure we are combining relevant memory
# operations correctly with/without DLC bit.
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
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@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s

# The purpose of this test is to make sure we are combining relevant memory
# operations correctly with/without SCC bit.
Expand Down
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