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[SelectionDAG][X86] Use getAllOnesConstant. NFC #104640

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Merged
merged 1 commit into from
Aug 17, 2024
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[SelectionDAG][X86] Use getAllOnesConstant. NFC #104640

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4390,7 +4390,7 @@ void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,

SDValue SatMax, SatMin;
SDValue NVTZero = DAG.getConstant(0, dl, NVT);
SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
SDValue NVTNeg1 = DAG.getAllOnesConstant(dl, NVT);
EVT BoolNVT = getSetCCResultType(NVT);

if (!Signed) {
Expand Down
19 changes: 10 additions & 9 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -23599,7 +23599,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,

if (!FlipSigns && !Invert && ISD::isBuildVectorAllOnes(Op1.getNode())) {
Op0 = DAG.getBitcast(MVT::v4i32, Op0);
Op1 = DAG.getConstant(-1, dl, MVT::v4i32);
Op1 = DAG.getAllOnesConstant(dl, MVT::v4i32);

SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
static const int MaskHi[] = { 1, 1, 3, 3 };
Expand Down Expand Up @@ -24391,7 +24391,7 @@ static SDValue LowerSIGN_EXTEND_Mask(SDValue Op, const SDLoc &dl,
(Subtarget.hasBWI() && WideEltVT.getSizeInBits() <= 16)) {
V = DAG.getNode(Op.getOpcode(), dl, WideVT, In);
} else {
SDValue NegOne = DAG.getConstant(-1, dl, WideVT);
SDValue NegOne = DAG.getAllOnesConstant(dl, WideVT);
SDValue Zero = DAG.getConstant(0, dl, WideVT);
V = DAG.getSelect(dl, WideVT, In, NegOne, Zero);
}
Expand Down Expand Up @@ -26095,7 +26095,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getOperand(3));
} else {
SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(1),
DAG.getConstant(-1, dl, MVT::i8));
DAG.getAllOnesConstant(dl, MVT::i8));
Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(2),
Op.getOperand(3), GenCF.getValue(1));
}
Expand Down Expand Up @@ -29378,7 +29378,7 @@ static SDValue LowerShiftByScalarVariable(SDValue Op, SelectionDAG &DAG,

// Create the mask using vXi16 shifts. For shift-rights we need to move
// the upper byte down before splatting the vXi8 mask.
SDValue BitMask = DAG.getConstant(-1, dl, ExtVT);
SDValue BitMask = DAG.getAllOnesConstant(dl, ExtVT);
BitMask = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, BitMask,
BaseShAmt, BaseShAmtIdx, Subtarget, DAG);
if (Opcode != ISD::SHL)
Expand Down Expand Up @@ -50580,7 +50580,7 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
// X - SETAE --> adc X, -1
return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
DAG.getVTList(VT, MVT::i32), X,
DAG.getConstant(-1, DL, VT), EFLAGS);
DAG.getAllOnesConstant(DL, VT), EFLAGS);
}

if (CC == X86::COND_BE) {
Expand All @@ -50601,7 +50601,7 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
SDValue NewEFLAGS = NewSub.getValue(EFLAGS.getResNo());
return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
DAG.getVTList(VT, MVT::i32), X,
DAG.getConstant(-1, DL, VT), NewEFLAGS);
DAG.getAllOnesConstant(DL, VT), NewEFLAGS);
}
}

Expand Down Expand Up @@ -50660,7 +50660,7 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
// X + (Z != 0) --> add X, (zext(setne Z, 0)) --> sbb X, -1, (cmp Z, 1)
if (CC == X86::COND_NE)
return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X,
DAG.getConstant(-1ULL, DL, VT), Cmp1.getValue(1));
DAG.getAllOnesConstant(DL, VT), Cmp1.getValue(1));

// X - (Z == 0) --> sub X, (zext(sete Z, 0)) --> sbb X, 0, (cmp Z, 1)
// X + (Z == 0) --> add X, (zext(sete Z, 0)) --> adc X, 0, (cmp Z, 1)
Expand Down Expand Up @@ -50944,8 +50944,9 @@ static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
EVT SetCCResultType = TLI.getSetCCResultType(DAG.getDataLayout(),
*DAG.getContext(), ResultType);
SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp,
DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
SDValue Cond =
DAG.getSetCC(DL, SetCCResultType, ShiftOp,
DAG.getAllOnesConstant(DL, ShiftOpTy), ISD::SETGT);
if (SetCCResultType != ResultType)
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, ResultType, Cond);
return Cond;
Expand Down
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