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[AMDGPU] Fix folding clamp into pseudo scalar instructions #100568

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Merged
mbrkusanin merged 3 commits into from
Jul 25, 2024
Merged

[AMDGPU] Fix folding clamp into pseudo scalar instructions #100568

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578adb3
[AMDGPU] Fix SIFoldOperands when folding clamp into pseudo scalar ins…
mbrkusanin Jul 25, 2024
ed083f0
fix typo
mbrkusanin Jul 25, 2024
e206cce
test update
mbrkusanin Jul 25, 2024
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13 changes: 12 additions & 1 deletion llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1581,7 +1581,18 @@ bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {

// Clamp is applied after omod, so it is OK if omod is set.
DefClamp->setImm(1);
MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());

Register DefReg = Def->getOperand(0).getReg();
Register MIDstReg = MI.getOperand(0).getReg();
if (TRI->isSGPRReg(*MRI, DefReg)) {
// Pseudo scalar instructions have a SGPR for dst and clamp is a v_max*
// instruction with a VGPR dst.
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY),
MIDstReg)
.addReg(DefReg);
} else {
MRI->replaceRegWith(MIDstReg, DefReg);
}
MI.eraseFromParent();

// Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac
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26 changes: 26 additions & 0 deletions llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
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@@ -0,0 +1,26 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
---
name: test
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0

; CHECK-LABEL: name: test
; CHECK: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_RSQ_F32_e64_:%[0-9]+]]:sgpr_32 = nofpexcept V_S_RSQ_F32_e64 0, [[COPY]], 1, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_S_RSQ_F32_e64_]]
; CHECK-NEXT: [[V_ADD_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e32 [[COPY1]], [[COPY1]], implicit $mode, implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_ADD_F32_e32_]]
; CHECK-NEXT: S_ENDPGM 0
%0:sgpr_32 = COPY $sgpr0
%1:sgpr_32 = nofpexcept V_S_RSQ_F32_e64 0, %0, 0, 0, implicit $mode, implicit $exec
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@arsenm arsenm Jul 25, 2024

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Why does this have a V_ prefix if it's just an S_ instruction?

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@mbrkusanin mbrkusanin Jul 25, 2024

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It is one of new pseudo scalar instructions. It behaves like SOP1 but it is actually a VOP3 and runs on VALU.

%2:vgpr_32 = nofpexcept V_MAX_F32_e64 0, %1, 0, %1, -1, 0, implicit $mode, implicit $exec
%3:vgpr_32 = nofpexcept V_ADD_F32_e32 %2:vgpr_32, %2:vgpr_32, implicit $mode, implicit $exec
$vgpr0 = COPY %3
S_ENDPGM 0

...