[RISCV] Rename merge operand -> passthru. NFC #100330
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@llvm/pr-subscribers-backend-risc-v Author: Luke Lau (lukel97) ChangesWe sometimes call the first tied dest operand in vector pseudos the merge operand, and other times the passthru. Passthru seems to be more common, and it's what the C intrinsics call it1, so this renames all usages of merge to passthru to be consistent. It also helps prevent confusion with vmerge.vvm in some of the peephole optimisations. Patch is 172.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/100330.diff 14 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index c0a4d0e9c520f..d9a6840a13aa8 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -975,7 +975,7 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
if (hasVLOutput && OpNo == 1)
continue;
- // Skip merge op. It should be the first operand after the defs.
+ // Skip passthru op. It should be the first operand after the defs.
if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 &&
"Expected tied to first def.");
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index eef6ae677ac85..2114bbe6d799f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3621,7 +3621,7 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
#endif
SmallVector<SDValue, 8> Ops;
- // Skip the merge operand at index 0 if !UseTUPseudo.
+ // Skip the passthru operand at index 0 if !UseTUPseudo.
for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) {
// Skip the mask, and the Glue.
SDValue Op = N->getOperand(I);
@@ -3684,9 +3684,9 @@ static unsigned GetVMSetForLMul(RISCVII::VLMUL LMUL) {
// ->
// %x = PseudoVADD_VV_MASK %false, ..., %mask
//
-// We can only fold if vmerge's merge operand, vmerge's false operand and
-// %true's merge operand (if it has one) are the same. This is because we have
-// to consolidate them into one merge operand in the result.
+// We can only fold if vmerge's passthru operand, vmerge's false operand and
+// %true's passthru operand (if it has one) are the same. This is because we
+// have to consolidate them into one passthru operand in the result.
//
// If %true is masked, then we can use its mask instead of vmerge's if vmerge's
// mask is all ones.
@@ -3697,12 +3697,12 @@ static unsigned GetVMSetForLMul(RISCVII::VLMUL LMUL) {
// The resulting VL is the minimum of the two VLs.
//
// The resulting policy is the effective policy the vmerge would have had,
-// i.e. whether or not it's merge operand was implicit-def.
+// i.e. whether or not it's passthru operand was implicit-def.
bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
- SDValue Merge, False, True, VL, Mask, Glue;
+ SDValue Passthru, False, True, VL, Mask, Glue;
// A vmv.v.v is equivalent to a vmerge with an all-ones mask.
if (IsVMv(N)) {
- Merge = N->getOperand(0);
+ Passthru = N->getOperand(0);
False = N->getOperand(0);
True = N->getOperand(1);
VL = N->getOperand(2);
@@ -3710,7 +3710,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
// mask later below.
} else {
assert(IsVMerge(N));
- Merge = N->getOperand(0);
+ Passthru = N->getOperand(0);
False = N->getOperand(1);
True = N->getOperand(2);
Mask = N->getOperand(3);
@@ -3721,9 +3721,9 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
assert(!Mask || cast<RegisterSDNode>(Mask)->getReg() == RISCV::V0);
assert(!Glue || Glue.getValueType() == MVT::Glue);
- // We require that either merge and false are the same, or that merge
+ // We require that either passthru and false are the same, or that passthru
// is undefined.
- if (Merge != False && !isImplicitDef(Merge))
+ if (Passthru != False && !isImplicitDef(Passthru))
return false;
assert(True.getResNo() == 0 &&
@@ -3753,11 +3753,11 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
if (!Info)
return false;
- // If True has a merge operand then it needs to be the same as vmerge's False,
- // since False will be used for the result's merge operand.
+ // If True has a passthru operand then it needs to be the same as vmerge's
+ // False, since False will be used for the result's passthru operand.
if (HasTiedDest && !isImplicitDef(True->getOperand(0))) {
- SDValue MergeOpTrue = True->getOperand(0);
- if (False != MergeOpTrue)
+ SDValue PassthruOpTrue = True->getOperand(0);
+ if (False != PassthruOpTrue)
return false;
}
@@ -3765,7 +3765,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
// 1s mask, since we're going to keep the mask from True.
if (IsMasked && Mask) {
// FIXME: Support mask agnostic True instruction which would have an
- // undef merge operand.
+ // undef passthru operand.
SDValue TrueMask =
getMaskSetter(True->getOperand(Info->MaskOpIdx),
True->getOperand(True->getNumOperands() - 1));
@@ -3823,8 +3823,8 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
return CLHS->getZExtValue() <= CRHS->getZExtValue() ? LHS : RHS;
};
- // Because N and True must have the same merge operand (or True's operand is
- // implicit_def), the "effective" body is the minimum of their VLs.
+ // Because N and True must have the same passthru operand (or True's operand
+ // is implicit_def), the "effective" body is the minimum of their VLs.
SDValue OrigVL = VL;
VL = GetMinVL(TrueVL, VL);
if (!VL)
@@ -3883,7 +3883,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
"Expected instructions with mask have a tied dest.");
#endif
- // Use a tumu policy, relaxing it to tail agnostic provided that the merge
+ // Use a tumu policy, relaxing it to tail agnostic provided that the passthru
// operand is undefined.
//
// However, if the VL became smaller than what the vmerge had originally, then
@@ -3891,7 +3891,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
// to the tail. In that case we always need to use tail undisturbed to
// preserve them.
bool MergeVLShrunk = VL != OrigVL;
- uint64_t Policy = (isImplicitDef(Merge) && !MergeVLShrunk)
+ uint64_t Policy = (isImplicitDef(Passthru) && !MergeVLShrunk)
? RISCVII::TAIL_AGNOSTIC
: /*TUMU*/ 0;
SDValue PolicyOp =
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d40d4997d7614..2dcdaa6194799 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3306,25 +3306,25 @@ static SDValue lowerVectorXRINT(SDValue Op, SelectionDAG &DAG,
static SDValue
getVSlidedown(SelectionDAG &DAG, const RISCVSubtarget &Subtarget,
- const SDLoc &DL, EVT VT, SDValue Merge, SDValue Op,
+ const SDLoc &DL, EVT VT, SDValue Passthru, SDValue Op,
SDValue Offset, SDValue Mask, SDValue VL,
unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) {
- if (Merge.isUndef())
+ if (Passthru.isUndef())
Policy = RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC;
SDValue PolicyOp = DAG.getTargetConstant(Policy, DL, Subtarget.getXLenVT());
- SDValue Ops[] = {Merge, Op, Offset, Mask, VL, PolicyOp};
+ SDValue Ops[] = {Passthru, Op, Offset, Mask, VL, PolicyOp};
return DAG.getNode(RISCVISD::VSLIDEDOWN_VL, DL, VT, Ops);
}
static SDValue
getVSlideup(SelectionDAG &DAG, const RISCVSubtarget &Subtarget, const SDLoc &DL,
- EVT VT, SDValue Merge, SDValue Op, SDValue Offset, SDValue Mask,
+ EVT VT, SDValue Passthru, SDValue Op, SDValue Offset, SDValue Mask,
SDValue VL,
unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) {
- if (Merge.isUndef())
+ if (Passthru.isUndef())
Policy = RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC;
SDValue PolicyOp = DAG.getTargetConstant(Policy, DL, Subtarget.getXLenVT());
- SDValue Ops[] = {Merge, Op, Offset, Mask, VL, PolicyOp};
+ SDValue Ops[] = {Passthru, Op, Offset, Mask, VL, PolicyOp};
return DAG.getNode(RISCVISD::VSLIDEUP_VL, DL, VT, Ops);
}
@@ -6092,8 +6092,8 @@ static unsigned getRISCVVLOp(SDValue Op) {
#undef VP_CASE
}
-/// Return true if a RISC-V target specified op has a merge operand.
-static bool hasMergeOp(unsigned Opcode) {
+/// Return true if a RISC-V target specified op has a passthru operand.
+static bool hasPassthruOp(unsigned Opcode) {
assert(Opcode > RISCVISD::FIRST_NUMBER &&
Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
@@ -10964,7 +10964,7 @@ SDValue RISCVTargetLowering::lowerVectorStrictFSetcc(SDValue Op,
True, VL});
Mask =
DAG.getNode(RISCVISD::VMAND_VL, DL, MaskVT, OrderMask1, OrderMask2, VL);
- // Use Mask as the merge operand to let the result be 0 if either of the
+ // Use Mask as the passthru operand to let the result be 0 if either of the
// inputs is unordered.
Res = DAG.getNode(RISCVISD::STRICT_FSETCCS_VL, DL,
DAG.getVTList(MaskVT, MVT::Other),
@@ -11069,7 +11069,7 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(
SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op,
SelectionDAG &DAG) const {
unsigned NewOpc = getRISCVVLOp(Op);
- bool HasMergeOp = hasMergeOp(NewOpc);
+ bool HasPassthruOp = hasPassthruOp(NewOpc);
bool HasMask = hasMaskOp(NewOpc);
MVT VT = Op.getSimpleValueType();
@@ -11094,7 +11094,7 @@ SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op,
SDLoc DL(Op);
auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
- if (HasMergeOp)
+ if (HasPassthruOp)
Ops.push_back(DAG.getUNDEF(ContainerVT));
if (HasMask)
Ops.push_back(Mask);
@@ -11122,7 +11122,7 @@ SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op,
// types.
SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
unsigned RISCVISDOpc = getRISCVVLOp(Op);
- bool HasMergeOp = hasMergeOp(RISCVISDOpc);
+ bool HasPassthruOp = hasPassthruOp(RISCVISDOpc);
SDLoc DL(Op);
MVT VT = Op.getSimpleValueType();
@@ -11135,9 +11135,9 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
for (const auto &OpIdx : enumerate(Op->ops())) {
SDValue V = OpIdx.value();
assert(!isa<VTSDNode>(V) && "Unexpected VTSDNode node!");
- // Add dummy merge value before the mask. Or if there isn't a mask, before
- // EVL.
- if (HasMergeOp) {
+ // Add dummy passthru value before the mask. Or if there isn't a mask,
+ // before EVL.
+ if (HasPassthruOp) {
auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode());
if (MaskIdx) {
if (*MaskIdx == OpIdx.index())
@@ -14652,25 +14652,25 @@ struct CombineResult {
/// The actual replacement is *not* done in that method.
SDValue materialize(SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) const {
- SDValue Mask, VL, Merge;
+ SDValue Mask, VL, Passthru;
std::tie(Mask, VL) =
NodeExtensionHelper::getMaskAndVL(Root, DAG, Subtarget);
switch (Root->getOpcode()) {
default:
- Merge = Root->getOperand(2);
+ Passthru = Root->getOperand(2);
break;
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
case ISD::OR:
case ISD::SHL:
- Merge = DAG.getUNDEF(Root->getValueType(0));
+ Passthru = DAG.getUNDEF(Root->getValueType(0));
break;
}
return DAG.getNode(TargetOpcode, SDLoc(Root), Root->getValueType(0),
LHS.getOrCreateExtendedOp(Root, DAG, Subtarget, LHSExt),
RHS.getOrCreateExtendedOp(Root, DAG, Subtarget, RHSExt),
- Merge, Mask, VL);
+ Passthru, Mask, VL);
}
};
@@ -16180,8 +16180,8 @@ static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
SDValue MulOp = N->getOperand(1);
if (N->getOpcode() == RISCVISD::ADD_VL) {
- SDValue AddMergeOp = N->getOperand(2);
- if (!AddMergeOp.isUndef())
+ SDValue AddPassthruOp = N->getOperand(2);
+ if (!AddPassthruOp.isUndef())
return SDValue();
}
@@ -16202,9 +16202,9 @@ static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
if (!IsVWMulOpc(MulOp.getOpcode()))
return SDValue();
- SDValue MulMergeOp = MulOp.getOperand(2);
+ SDValue MulPassthruOp = MulOp.getOperand(2);
- if (!MulMergeOp.isUndef())
+ if (!MulPassthruOp.isUndef())
return SDValue();
auto [AddMask, AddVL] = [](SDNode *N, SelectionDAG &DAG,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index e469a4b1238c7..06b4edc5b479a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -237,7 +237,7 @@ enum NodeType : unsigned {
VECREDUCE_FMIN_VL,
VECREDUCE_FMAX_VL,
- // Vector binary ops with a merge as a third operand, a mask as a fourth
+ // Vector binary ops with a passthru as a third operand, a mask as a fourth
// operand, and VL as a fifth operand.
ADD_VL,
AND_VL,
@@ -293,7 +293,7 @@ enum NodeType : unsigned {
FABS_VL,
FSQRT_VL,
FCLASS_VL,
- FCOPYSIGN_VL, // Has a merge operand
+ FCOPYSIGN_VL, // Has a passthru operand
VFCVT_RTZ_X_F_VL,
VFCVT_RTZ_XU_F_VL,
VFCVT_X_F_VL,
@@ -321,7 +321,7 @@ enum NodeType : unsigned {
VFWMSUB_VL,
VFWNMSUB_VL,
- // Widening instructions with a merge value a third operand, a mask as a
+ // Widening instructions with a passthru value a third operand, a mask as a
// fourth operand, and VL as a fifth operand.
VWMUL_VL,
VWMULU_VL,
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 96250b9c03b79..7b79026d30807 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -182,7 +182,7 @@ static bool isMaskRegOp(const MachineInstr &MI) {
/// Note that this is different from "agnostic" as defined by the vector
/// specification. Agnostic requires each lane to either be undisturbed, or
/// take the value -1; no other value is allowed.
-static bool hasUndefinedMergeOp(const MachineInstr &MI) {
+static bool hasUndefinedPassthru(const MachineInstr &MI) {
unsigned UseOpIdx;
if (!MI.isRegTiedToUseOperand(0, &UseOpIdx))
@@ -443,13 +443,13 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
Res.LMUL = DemandedFields::LMULNone;
Res.SEWLMULRatio = false;
Res.VLAny = false;
- // For vmv.s.x and vfmv.s.f, if the merge operand is *undefined*, we don't
+ // For vmv.s.x and vfmv.s.f, if the passthru is *undefined*, we don't
// need to preserve any other bits and are thus compatible with any larger,
// etype and can disregard policy bits. Warning: It's tempting to try doing
// this for any tail agnostic operation, but we can't as TA requires
// tail lanes to either be the original value or -1. We are writing
// unknown bits to the lanes here.
- if (hasUndefinedMergeOp(MI)) {
+ if (hasUndefinedPassthru(MI)) {
if (isFloatScalarMoveOrScalarSplatInstr(MI) && !ST->hasVInstructionsF64())
Res.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
else
@@ -469,7 +469,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
if (RISCVII::hasVLOp(MI.getDesc().TSFlags)) {
const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
- // A slidedown/slideup with an *undefined* merge op can freely clobber
+ // A slidedown/slideup with an *undefined* passthru can freely clobber
// elements not copied from the source vector (e.g. masked off, tail, or
// slideup's prefix). Notes:
// * We can't modify SEW here since the slide amount is in units of SEW.
@@ -478,7 +478,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
// * The LMUL1 restriction is for machines whose latency may depend on VL.
// * As above, this is only legal for tail "undefined" not "agnostic".
if (isVSlideInstr(MI) && VLOp.isImm() && VLOp.getImm() == 1 &&
- hasUndefinedMergeOp(MI)) {
+ hasUndefinedPassthru(MI)) {
Res.VLAny = false;
Res.VLZeroness = true;
Res.LMUL = DemandedFields::LMULLessThanOrEqualToM1;
@@ -492,7 +492,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
// careful to not increase the number of active vector registers (unlike for
// vmv.s.x.)
if (isScalarSplatInstr(MI) && VLOp.isImm() && VLOp.getImm() == 1 &&
- hasUndefinedMergeOp(MI)) {
+ hasUndefinedPassthru(MI)) {
Res.LMUL = DemandedFields::LMULLessThanOrEqualToM1;
Res.SEWLMULRatio = false;
Res.VLAny = false;
@@ -1000,7 +1000,7 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const {
bool TailAgnostic = true;
bool MaskAgnostic = true;
- if (!hasUndefinedMergeOp(MI)) {
+ if (!hasUndefinedPassthru(MI)) {
// Start with undisturbed.
TailAgnostic = false;
MaskAgnostic = false;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index b5817237b7fd2..5580504061637 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -92,34 +92,34 @@ def simm5_plus1_nonzero : ImmLeaf<XLenVT,
//===----------------------------------------------------------------------===//
// Common class of scheduling definitions.
-// `ReadVMergeOp` will be prepended to reads if instruction is masked.
+// `ReadVPassthru` will be prepended to reads if instruction is masked.
// `ReadVMask` will be appended to reads if instruction is masked.
// Operands:
// `writes` SchedWrites that are listed for each explicit def operand
// in order.
// `reads` SchedReads that are listed for each explicit use operand.
// `forceMasked` Forced to be masked (e.g. Add-with-Carry Instructions).
-// `forceMergeOpRead` Force to have read for merge operand.
+// `forcePassthruRead` Force to have read for passthru operand.
class SchedCommon<list<SchedWrite> writes, list<SchedRead> reads,
string mx = "WorstCase", int sew = 0, bit forceMasked = 0,
- bit forceMergeOpRead = 0> : Sched<[]> {
+ bit forcePassthruRead = 0> : Sched<[]> {
defvar isMasked = !ne(!find(NAME, "_MASK"), -1);
defvar isMaskedOrForceMasked = !or(forceMasked, isMasked);
- defvar mergeRead = !if(!or(!eq(mx, "WorstCase"), !eq(sew, 0)),
- !cast<SchedRead>("ReadVMergeOp_" # mx),
- !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" #sew));
- defvar needsMergeRead = !or(isMaskedOrForceMasked, forceMergeOpRead);
+ defvar passthruRead = !if(!or(!eq(mx, "WorstCase"), !eq(sew, 0)),
+ !cast<SchedRead>("ReadVPassthru_" # mx),
+ !cast<SchedRead>("ReadVPassthru_" # mx # "_E" #sew));
+ defvar needsPassthruRead = !or(isMaskedOrForceMasked, forcePassthruRead);
defvar readsWithMask =
!if(isMaskedOrForceMasked, !listconcat(reads, [ReadVMask]), reads);
defvar allReads =
- !if(needsMergeRead, !listconcat([mergeRead], readsWithMask), reads);
+ !if(needsPassthruRead, !listconcat([passthruRead], readsWithMask), reads);
let SchedRW = !listconcat(writes, allReads);
}
// Common class of scheduling definitions for n-ary instructions.
// The scheudling resources are relevant to LMUL and may be relevant to SEW.
class SchedNary<string write, list<string> reads, string mx, int sew = 0,
- bit forceMasked = 0, bit forceMergeOpRead = 0>
+ bit forceMasked = 0, bit forcePassthruRead = 0>
: SchedCommon<[!cast<SchedWrite>(
!if(sew,
write # "_" # mx # "_E" # sew,
@@ -127,7 +127,7 @@ class SchedNary<string write, list<string> reads, string mx, int sew = 0,
!foreach(read, reads,
!cast<SchedRead>(!if(sew, read #"_" #mx #"_E" #sew,
read #"_" #mx))),
- mx, sew, forceMasked, forceMergeOpRead>;
+ mx, sew, forceMasked, forcePassthruRead>;
// Classes with postfix "MC" are only used in MC layer.
// For these classes, we assume that they are with the worst case costs and
@@ -135,22 +135,22 @@ cl...
[truncated]
Footnotes |
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We sometimes call the first tied dest operand in vector pseudos the merge operand, and other times the passthru. Passthru seems to be more common, and it's what the C intrinsics call it[^1], so this renames all usages of merge to passthru to be consistent. It also helps prevent confusion with vmerge.vvm in some of the peephole optimisations. [^1]: https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#the-passthrough-vd-argument-in-the-intrinsics
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We sometimes call the first tied dest operand in vector pseudos the merge operand, and other times the passthru.
Passthru seems to be more common, and it's what the C intrinsics call it1, so this renames all usages of merge to passthru to be consistent. It also helps prevent confusion with vmerge.vvm in some of the peephole optimisations.
Footnotes
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#the-passthrough-vd-argument-in-the-intrinsics ↩