Assertion fail: "This value type is not natively supported!"

[dcb314]

llvm $ source ./sha512-9ba5ba.sh
clang-19: /home/dcb38/llvm/trunk/llvm/include/llvm/CodeGen/TargetLowering.h:1025: virtual const llvm::TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor(llvm::MVT, bool) const: Assertion `RC && "This value type is not natively supported!"' failed.

sha512-9ba5ba.c.gz
sha512-9ba5ba.sh.gz

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: None (dcb314)

llvm $ source ./sha512-9ba5ba.sh clang-19: /home/dcb38/llvm/trunk/llvm/include/llvm/CodeGen/TargetLowering.h:1025: virtual const llvm::TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor(llvm::MVT, bool) const: Assertion `RC && "This value type is not natively supported!"' failed.

sha512-9ba5ba.c.gz
sha512-9ba5ba.sh.gz

[RKSimon]

Reduced:

define void @PR90844() #0 {
entry:
  %0 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i32> <i32 8, i32 24>)
  %1 = and <2 x i32> %0, <i32 16711935, i32 -134152448>
  %2 = or disjoint <2 x i32> zeroinitializer, %1
  %3 = zext <2 x i32> %2 to <2 x i64>
  %4 = shl nuw <2 x i64> %3, <i64 32, i64 32>
  %5 = or disjoint <2 x i64> %4, zeroinitializer
  store <2 x i64> %5, ptr poison, align 16
  ret void
}
attributes #0 = { "target-features"="+64bit,+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512ifma,+avx512vbmi2,+bmi,+bmi2,+clflushopt,+clwb,+clzero,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mwaitx,+pclmul,+pku,+popcnt,+prfchw,+rdpid,+rdpru,+rdrnd,+rdseed,+sahf,+sha,+shstk,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3,+vaes,+vpclmulqdq,+wbnoinvd,+x87,+xsave,+xsavec,+xsaveopt,+xsaves,-amx-bf16,-amx-complex,-amx-fp16,-amx-int8,-amx-tile,-avx10.1-256,-avx10.1-512,-avx512bf16,-avx512bitalg,-avx512er,-avx512fp16,-avx512pf,-avx512vbmi,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-ccmp,-cf,-cldemote,-cmpccxadd,-egpr,-enqcmd,-evex512,-fma4,-gfni,-hreset,-kl,-lwp,-movdir64b,-movdiri,-ndd,-pconfig,-ppx,-prefetchi,-prefetchwt1,-ptwrite,-push2pop2,-raoint,-rtm,-serialize,-sgx,-sha512,-sm3,-sm4,-tbm,-tsxldtrk,-uintr,-usermsr,-waitpkg,-widekl,-xop" }

@dcb314 what -march= setting did you originally use? the script just shows a mix of raw attributes that AFAICT doesn't think matches any avx512 cpu.

[RKSimon]

Optimized legalized selection DAG: %bb.0 'PR90844:entry'
SelectionDAG has 17 nodes:
  t0: ch,glue = EntryToken
        t39: v4i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>
              t48: i64 = X86ISD::Wrapper TargetConstantPool:i64<<4 x i32> <i32 8, i32 24, i32 undef, i32 undef>> 0
            t46: v4i32,ch = load<(load (s128) from constant-pool)> t0, t48, undef:i64
          t30: v4i32 = rotl undef:v4i32, t46
            t50: i64 = X86ISD::Wrapper TargetConstantPool:i64<<4 x i32> <i32 16711935, i32 -134152448, i32 undef, i32 undef>> 0
          t44: v4i32,ch = load<(load (s128) from constant-pool)> t0, t50, undef:i64
        t31: v4i32 = and t30, t44
      t40: v4i32 = X86ISD::UNPCKL t39, t31
    t42: ch = store<(store (s128) into `ptr poison`)> t0, t40, undef:i64, undef:i64
  t23: ch = X86ISD::RET_GLUE t42, TargetConstant:i32<0>

Selected selection DAG: %bb.0 'PR90844:entry'
SelectionDAG has 22 nodes:
  t0: ch,glue = EntryToken
              t58: v16i32 = INSERT_SUBREG IMPLICIT_DEF:v16i32, IMPLICIT_DEF:v4i32, TargetConstant:i32<9>
                t46: v4i32,ch = VMOVDQArm<Mem:(load (s128) from constant-pool)> Register:i64 $rip, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstantPool:i32<<4 x i32> <i32 8, i32 24, i32 undef, i32 undef>> 0, Register:i16 $noreg, t0
              t59: v16i32 = INSERT_SUBREG IMPLICIT_DEF:v16i32, t46, TargetConstant:i32<9>
            t60: v16i32 = VPROLVDZrr t58, t59
          t30: v4i32 = EXTRACT_SUBREG t60, TargetConstant:i32<9>
        t31: v4i32,ch = VPANDrm<Mem:(load (s128) from constant-pool)> t30, Register:i64 $rip, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstantPool:i32<<4 x i32> <i32 16711935, i32 -134152448, i32 undef, i32 undef>> 0, Register:i16 $noreg, t0
      t40: v4i32 = VPUNPCKLDQrr AVX512_128_SET0:v4i32, t31
    t42: ch = VMOVDQAmr<Mem:(store (s128) into `ptr poison`)> IMPLICIT_DEF:i64, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t40, t0
  t23: ch = RET TargetConstant:i32<0>, t42

[phoebewang]

In the script sha512-9ba5ba.sh, we can find the target is znver3 with -evex512 and -avx512vl:

"-target-cpu" "znver3" ... "-target-feature" "-evex512" ... "-target-feature" "-avx512vl"

This probably a mis-combination of options, though compiler shouldn't crash in this case. Create for #91106 this.