[AArch64] Optimize the offset of memory access

[vfdff]

• test: https://gcc.godbolt.org/z/nhYcWq1WE

int testOffset(char a[]) {
  return a[0xfde78];
}

• gcc:

testOffset(char*):
        add     x0, x0, 1036288
        ldrb    w0, [x0, 3704]
        ret

• llvm:

testOffset(char*):                       // @testOffset(char*)
        mov     w8, #56952                      // =0xde78
        movk    w8, #15, lsl #16
        ldrb    w0, [x0, x8]
        ret

• Gcc using base addressing produces more efficient instructions than llvm using index addressing.

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Allen (vfdff)

* test: https://gcc.godbolt.org/z/nhYcWq1WE ``` int testOffset(char a[]) { return a[0xfde78]; } ``` * gcc: ``` testOffset(char*): add x0, x0, 1036288 ldrb w0, [x0, 3704] ret ``` * llvm: ``` testOffset(char*): // @testOffset(char*) mov w8, #56952 // =0xde78 movk w8, #15, lsl #16 ldrb w0, [x0, x8] ret ```

• Gcc using base addressing produces more efficient instructions than llvm using index addressing.

[vfdff]

• its related IR

define i32 @testOffset(ptr nocapture noundef readonly %a)  {
entry:
  %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
  %0 = load i8, ptr %arrayidx, align 1
  %conv = zext i8 %0 to i32
  ret i32 %conv
}