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[AArch64] GlobalIsel unable to legalize vectorized binaryop(G_ADD, G_SUB, ...) #58156
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@llvm/issue-subscribers-backend-aarch64 |
Sorry for not responding to this, I'd missed it. Thanks for the report. I think your analysis is generally correct, this is just missing functionality. |
CarlosAlbertoEnciso
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Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors. Fixes llvm/llvm-project#58156. Differential Revision: https://reviews.llvm.org/D143517
veselypeta
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Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors. Fixes llvm/llvm-project#58156. Differential Revision: https://reviews.llvm.org/D143517
veselypeta
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Aug 15, 2024
Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors. Fixes llvm/llvm-project#58156. Differential Revision: https://reviews.llvm.org/D143517
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Our aflplusplus fuzzing shows that AArch64 can't compile the following code can't compile using
llc -mtriple=aarch64 -global-isel add.ll
, It could complaint:unable to legalize instruction: %10:_(<32 x s16>) = G_ADD %0:_, %1:_ (in function: add_32xi16)
Godbolt: https://godbolt.org/z/7rz7WdbEx
A further study shows that in
AArch64LegalizeInfo.cpp:116
Many vectorized operations are not legal for all five operations.
It seems to us that we should be using the following diff:
However, many tests failed after we make this change. It seems many other places need to switch from
clampScalar
toclampScalarOrElt
to include vector types.Is this a feature, where we don't want certain vector types to get compiled; or this is a bug.
If it is a feature, can anyone elaborate why do we design it like this? If it is a bug, we can make some quick fixes.
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