[mca][x86] Test coverage for conversion instructions is not full

[LebedevRI]

Bugzilla Link	41799
Version	trunk
OS	Linux
CC	@adibiagio,@topperc,@RKSimon

Extended Description

Noticed by accident.
E.g. CVTSI642SDrr, CVTSI642SSrr, CVTSI2SDrr, CVTSI2SSrr have no coverage.
At least changing the schedule does not result in any mca test changes

[adibiagio]

Since r358138 (https://llvm.org/viewvc/llvm-project?view=revision&revision=358138)
the assembly parser use the _Int variants for those instructions.

Example:

test.s

cvtsi2ss %eax, %xmm0
cvtsi2sd %eax, %xmm0
cvtsi2sd %rax, %xmm0
cvtsi2ss %rax, %xmm0

llvm-mc test.s -show-inst

        .text
        cvtsi2ss        %eax, %xmm0     # <MCInst #&#8203;777 CVTSI2SSrr_Int
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:22>>
        cvtsi2sd        %eax, %xmm0     # <MCInst #&#8203;773 CVTSI2SDrr_Int
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:22>>
        cvtsi2sd        %rax, %xmm0     # <MCInst #&#8203;781 CVTSI642SDrr_Int
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:48>>
        cvtsi2ss        %rax, %xmm0     # <MCInst #&#8203;785 CVTSI642SSrr_Int
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:142>
                                        #  <MCOperand Reg:48>>

[topperc]

Ideally we'd test both forms. Not sure how to do that from the assembly parsing without introducing some way of specifying the other instruction. Is there something we can do with a MIR or LL file?

[adibiagio]

Ideally we'd test both forms. Not sure how to do that from the assembly
parsing without introducing some way of specifying the other instruction. Is
there something we can do with a MIR or LL file?

It would be nice to be able to analyze MIR to verify latency/throughput. However, that feature doesn't exist at the moment.