LLVM fails to reduce zext(op(zext)) in some cases

[AZero13]

In the benchmark, I noticed

%30 = zext i16 %.promoted47 to i32
%31 = mul nuw nsw i32 %30, 20
%32 = zext nneg i32 %31 to i64

%31 is not used at all elsewhere.

It should be

%30 = zext i16 %.promoted47 to i64
%31 = mul nuw nsw i64 %30, 20

https://alive2.llvm.org/ce/z/XpJe59

I noticed that LLVM did in fact do this properly when I did an unrelated change: #140178

But that is because the DAG was different, meaning there is an edge case where this is not happening when it should be.

[AZero13]

See: dtcxzyw/llvm-opt-benchmark#2366

[RKSimon]

it might be worth doing this canonicalization in instcombine, but we need the DAG to do a better job of ensuring we avoid unnecessary extended (in this case i64) arithmetic:

src: # @src
  movzwl %di, %eax
  shll $2, %eax
  leal (%rax,%rax,4), %eax
  retq
tgt: # @tgt
  movzwl %di, %eax
  shll $2, %eax
  leaq (%rax,%rax,4), %rax
  retq

That LEA case isn't too bad, but if we lower to mul it can start hurting us:

define i64 @src(i16 %a) {
#0:
  %#1 = zext i16 %a to i32
  %#2 = mul nsw nuw i32 %#1, 49
  %#3 = zext nneg i32 %#2 to i64
  ret i64 %#3
}
=>
define i64 @tgt(i16 %a) {
#0:
  %#1 = zext i16 %a to i64
  %#2 = mul nsw nuw i64 %#1, 49
  ret i64 %#2
}

src: # @src
  movzwl %di, %eax
  imull $49, %eax, %eax
  retq
tgt: # @tgt
  movzwl %di, %eax
  imulq $49, %rax, %rax
  retq