Open
Description
https://godbolt.org/z/K5K6f9918
https://alive2.llvm.org/ce/z/SicZdr
The reduced IR is derived from https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/356d0047122531ffd8b2b7410f7f3c8c17db78e6/abc/src/base/abci/abcOrchestration.c#L2666
For the following code, through control flow, it can be deduced that %1 is always false in block %6, but LLVM fails to leverage this fact to optimize store i1 %1, ptr %0, align 4
define noundef i32 @src(ptr %0, i1 %1, i1 %2) local_unnamed_addr {
br i1 %2, label %4, label %5
4:
br i1 %1, label %common.ret, label %5
5:
br i1 %2, label %6, label %common.ret
common.ret:
ret i32 0
6:
store i1 %1, ptr %0, align 4
br label %common.ret
}
opt -O3:
define noundef i32 @src(ptr writeonly captures(none) %0, i1 %1, i1 %2) local_unnamed_addr #0 {
%.not = xor i1 %2, true
%4 = select i1 %2, i1 %1, i1 false
%brmerge3 = or i1 %4, %.not
br i1 %brmerge3, label %common.ret, label %5
common.ret:
ret i32 0
5:
store i1 %1, ptr %0, align 4
br label %common.ret
}
expected:
define noundef i32 @src(ptr writeonly captures(none) %0, i1 %1, i1 %2) local_unnamed_addr #0 {
%.not = xor i1 %2, true
%4 = select i1 %2, i1 %1, i1 false
%brmerge3 = or i1 %4, %.not
br i1 %brmerge3, label %common.ret, label %5
common.ret:
ret i32 0
5:
store i1 false, ptr %0, align 4
br label %common.ret
}