Open
Description
At first glance, I see:
bb.1 (%ir-block.1):
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
...
renamable $r0l = LOCHIMux killed renamable $r0l(tied-def 0), 1, 14, 4, implicit killed $cc
renamable $r2d = LARL @d
STCMux renamable $r0l, killed renamable $r2d, 0, $noreg :: (store (s8) into @d, align 2)
STMux killed renamable $r0l, killed renamable $r1d, 0, $noreg :: (volatile store (s32) into %ir.2)
J %bb.3
bb.2 (%ir-block.7):
; predecessors: %bb.0
successors: %bb.3(0x80000000); %bb.3(100.00%)
renamable $r0l = LHIMux 0
renamable $r0l = LOCHIMux killed renamable $r0l(tied-def 0), 1, 14, 4, implicit killed $cc
renamable $r2d = LARL @b
STCMux killed renamable $r0l, killed renamable $r2d, 0, $noreg :: (store (s8) into @b, align 2)
STMux undef renamable $r0l, killed renamable $r1d, 0, $noreg :: (volatile store (s32) into %ir.8)
=>
# *** IR Dump After Control Flow Optimizer (branch-folder) ***:
...
bb.3 (%ir-block.12):
; predecessors: %bb.2, %bb.1
liveins: $r0l, $r1d, $r2d
STCMux killed renamable $r0l, killed renamable $r2d, 0, $noreg :: (store (s8) into @b, align 2), (store (s8) into @d, align 2)
STMux renamable $r0l, killed renamable $r1d, 0, $noreg :: (volatile store (s32) into %ir.8), (volatile store (s32) into %ir.2)
Return
*** Bad machine code: Using an undefined physical register ***
- function: n
- basic block: %bb.3 (0x2aa047384c8)
- instruction: STMux renamable $r0l, killed renamable $r1d, 0, $noreg :: (volatile store (s32) into %ir.8), (volatile store (s32) into %ir.2)
- operand 0: renamable $r0l
LLVM ERROR: Found 1 machine code errors.
Somehow the kill and undef flags have been combined into an illegal sequence where $r0l is used after a kill. @arsenm Once again, the maintaining of kill flags are coming back...
@dominik-steenken This is the reduced test case, so not sure if the storing of undef is a bug, but probably not. Attaching also the original .i file and the reduced .i file.
clang -O3 -march=z15 crash10.orig.i -o a.out -w -mllvm -enable-unswitch-cost-multiplier=false -mllvm -sink-common-insts -mllvm -aggressive-machine-cse -mllvm -verify-misched
llc -mcpu=z15 -O3 -verify-machineinstrs tc_crash10_aftercreduce.ll