[AArch64] `clz` on u8/u16 unnecessarily zero-extended to u32

[Kmeakin]

The result of the clz instruction on an 8-bit or 16-bit value is unecessarily zero-extended to 32-bits via and

C++ example

https://godbolt.org/z/rc9P4a54a

#include <cstdint>

using u8 = uint8_t;
using u16 = uint16_t;
using u32 = uint32_t;
using u64 = uint64_t;
using u128 = __uint128_t;

auto src8(u8 x) { return __builtin_clzg(x); }
auto src16(u16 x) { return __builtin_clzg(x); }

Clang assembly

src8(unsigned char):
        and     w8, w0, #0xff
        clz     w8, w8
        sub     w8, w8, #24
        and     w0, w8, #0xff
        ret

src16(unsigned short):
        and     w8, w0, #0xffff
        clz     w8, w8
        sub     w8, w8, #16
        and     w0, w8, #0xffff
        ret

GCC assembly

src8(unsigned char):
        and     w0, w0, 255
        clz     w0, w0
        sub     w0, w0, #24
        ret
src16(unsigned short):
        and     w0, w0, 65535
        clz     w0, w0
        sub     w0, w0, #16
        ret

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Karl Meakin (Kmeakin)

The result of the `clz` instruction on an 8-bit or 16-bit value is unecessarily zero-extended to 32-bits via `and`

C++ example

https://godbolt.org/z/rc9P4a54a

#include <cstdint>

using u8 = uint8_t;
using u16 = uint16_t;
using u32 = uint32_t;
using u64 = uint64_t;
using u128 = __uint128_t;

auto src8(u8 x) { return __builtin_clzg(x); }
auto src16(u16 x) { return __builtin_clzg(x); }

Clang assembly

src8(unsigned char):
        and     w8, w0, #<!-- -->0xff
        clz     w8, w8
        sub     w8, w8, #<!-- -->24
        and     w0, w8, #<!-- -->0xff
        ret

src16(unsigned short):
        and     w8, w0, #<!-- -->0xffff
        clz     w8, w8
        sub     w8, w8, #<!-- -->16
        and     w0, w8, #<!-- -->0xffff
        ret

GCC assembly

src8(unsigned char):
        and     w0, w0, 255
        clz     w0, w0
        sub     w0, w0, #<!-- -->24
        ret
src16(unsigned short):
        and     w0, w0, 65535
        clz     w0, w0
        sub     w0, w0, #<!-- -->16
        ret

[davemgreen]

We have different results to X86 as AArch64 sets isCLZForZeroUndef() to false. That uses a ctlz as opposed to ctlz_zero_undef which prevents some optimizations that would otherwise happen. The intrinsics are defined to return an undefined result if no second parameter is set so maybe this is not required.

With a defined result for zero, SDAG looks like:

          t2: i32,ch = CopyFromReg t0, Register:i32 %0
        t4: i32 = AssertZext t2, ValueType:ch:i8
      t13: i32 = and t4, Constant:i32<255>
    t14: i32 = ctlz t13
  t15: i32 = sub t14, Constant:i32<24>
t16: i32 = and t15, Constant:i32<255>

It could presumably know that the (ctlz (and 255)) is in the range 24-32, so sub (ctlz (and 255)), 24 is in the range 0-8, and so all the high bits are zero. So the known bits of t15 are all zero in the upper bits, so the and can be removed. The intrinsic has range metadata but it doesn't make it into DAG.