[x86-64 BMI1] Missed `blsi` emit when `& x` can be unnecessarily factored out of `(x & -x)`

[Validark]

This code: (Zig Godbolt) (LLVM Godbolt)

export fn z(b: bool, x: u64) u64 {
    const y = x & -%x; // blsi
    return if (b) y else x;
}

Gives:

        mov     rcx, rsi
        neg     rcx
        test    edi, edi
        mov     rax, -1
        cmovne  rax, rcx
        and     rax, rsi

It should be:

        blsi    rax, rsi
        test    edi, edi
        cmove   rax, rsi

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Niles Salter (Validark)

This code: ([Zig Godbolt](https://zig.godbo.lt/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:14,fontUsePx:'0',j:1,lang:zig,selection:(endColumn:1,endLineNumber:11,positionColumn:1,positionLineNumber:11,selectionStartColumn:1,selectionStartLineNumber:11,startColumn:1,startLineNumber:11),source:'export+fn+z(b:+bool,+x:+u64)+u64+%7B%0A++++const+y+%3D+x+%26+-%25x%3B+//+blsi%0A++++return+if+(b)+y+else+x%3B%0A%7D%0A%0Aexport+fn+z2(b:+bool,+x:+u64)+u64+%7B%0A++++const+y+%3D+blsi(x)%3B%0A++++return+if+(b)+y+else+x%3B%0A%7D%0A%0Afn+blsi(a:+u64)+u64+%7B%0A++++return+asm+(%22blsi+%25%5Ba%5D,+%25%5Bret%5D%22%0A++++++++:+%5Bret%5D+%22%3Dr%22+(-%3E+u64),%0A++++++++:+%5Ba%5D+%22r%22+(a),%0A++++)%3B%0A%7D'),l:'5',n:'0',o:'Zig+source+%231',t:'0')),k:50,l:'4',n:'0',o:'',s:0,t:'0'),(g:!((h:compiler,i:(compiler:ztrunk,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:14,fontUsePx:'0',j:2,lang:zig,libs:!(),options:'-O+ReleaseFast+-target+x86_64-linux+-mcpu%3Dznver5',overrides:!(),selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),source:1),l:'5',n:'0',o:'+zig+trunk+(Editor+%231)',t:'0')),header:(),k:50,l:'4',m:100,n:'0',o:'',s:0,t:'0')),l:'2',n:'0',o:'',t:'0')),version:4)) ([LLVM Godbolt](https://llvm.godbo.lt/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:14,fontUsePx:'0',j:1,lang:llvm,selection:(endColumn:1,endLineNumber:21,positionColumn:1,positionLineNumber:21,selectionStartColumn:1,selectionStartLineNumber:21,startColumn:1,startLineNumber:21),source:'define+dso_local+i64+@z(i1+zeroext+%250,+i64+%251)+local_unnamed_addr+%7B%0AEntry:%0A++%252+%3D+sub+i64+0,+%251%0A++%253+%3D+select+i1+%250,+i64+%252,+i64+-1%0A++%25.+%3D+and+i64+%253,+%251%0A++ret+i64+%25.%0A%7D%0A%0Adefine+dso_local+i64+@z2(i1+zeroext+%250,+i64+%251)+local_unnamed_addr+%7B%0AEntry:%0A++%252+%3D+tail+call+i64+asm+%22blsi+$%7B1%7D,+$%7B0%7D%22,+%22%3Dr,r,~%7Bdirflag%7D,~%7Bfpsr%7D,~%7Bflags%7D%22(i64+%251)+%232%0A++%25.+%3D+select+i1+%250,+i64+%252,+i64+%251%0A++ret+i64+%25.%0A%7D%0A%0Adefine+dso_local+i64+@blsi(i64+%250)+local_unnamed_addr+%7B%0AEntry:%0A++%251+%3D+tail+call+i64+asm+%22blsi+$%7B1%7D,+$%7B0%7D%22,+%22%3Dr,r,~%7Bdirflag%7D,~%7Bfpsr%7D,~%7Bflags%7D%22(i64+%250)+%232%0A++ret+i64+%251%0A%7D%0A'),l:'5',n:'0',o:'LLVM+IR+source+%231',t:'0')),k:48.76712328767123,l:'4',n:'0',o:'',s:0,t:'0'),(g:!((h:compiler,i:(compiler:irclangtrunk,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:14,fontUsePx:'0',j:1,lang:llvm,libs:!(),options:'-O3+-march%3Dznver5',overrides:!(),selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),source:1),l:'5',n:'0',o:'+clang+(trunk)+(Editor+%231)',t:'0')),k:51.23287671232877,l:'4',m:100,n:'0',o:'',s:0,t:'0')),l:'2',n:'0',o:'',t:'0')),version:4))

export fn z(b: bool, x: u64) u64 {
    const y = x & -%x; // blsi
    return if (b) y else x;
}

Gives:

        mov     rcx, rsi
        neg     rcx
        test    edi, edi
        mov     rax, -1
        cmovne  rax, rcx
        and     rax, rsi

It should be:

        blsi    rax, rsi
        test    edi, edi
        cmove   rax, rsi

[RKSimon]

define i64 @z(i1 zeroext %0, i64 %1) {
Entry:
  %2 = sub i64 0, %1
  %3 = select i1 %0, i64 %2, i64 -1
  %. = and i64 %3, %1
  ret i64 %.
}

[RKSimon]

----------------------------------------
define i4 @src(i1 zeroext %a0, i4 %a1) {
#0:
  %sub = sub i4 0, %a1
  %sel = select i1 zeroext %a0, i4 %sub, i4 15
  %ret = and i4 %sel, %a1
  ret i4 %ret
}
=>
define i4 @tgt(i1 zeroext %a0, i4 %a1) {
#0:
  %sub = sub i4 0, %a1
  %bls = and i4 %sub, %a1
  %ret = select i1 zeroext %a0, i4 %bls, i4 %a1
  ret i4 %ret
}
Transformation seems to be correct!

[Validark]

To be clear, I am talking about undoing an optimization LLVM is doing. I wrote this:

export fn z(b: bool, x: u64) u64 {
    const y = x & -%x; // blsi
    return if (b) y else x;
}

And LLVM wrote this:

export fn z(b: bool, x: u64) u64 {
    const y = -%x;
    return (if (b) y else -1) & x;
}

[RKSimon]

Yes, its a instcombine canonicalisation that we should be able to undo in the backend if we're careful.