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AMDGPU inreg arguments for SGPRs use whole VGPRs after SGPR arguments run out #129071

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@arsenm

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@arsenm

When SGPR available for argument passing run out, they silently switch to using whole VGPRs to pass arguments.

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -o - %s

target triple = "amdgcn-amd-amdhsa"

define i32 @test0(<8 x i32> inreg %arg0,
                  <8 x i32> inreg %arg1,
                  <2 x i32> inreg %arg2,
                  i32 inreg %arg3,
                  i32 inreg %arg4) {
  %add = add i32 %arg3, %arg4 ; arg3 is v0, arg4 is in v1. These should be packed into a lane and extracted with readlane
  ret i32 %add
}

Ideally we would start to pack inreg arguments into individual lanes of VGPRs, not directly into VGPRs.

In this example, we ran out of SGPRs after 18 arguments. %arg3 and %arg4 end up in v0 and v1. We could treat these as WWM values, and pass them in v0.lane0 and v0.lane1.

Either way, we should get a scalar value in downstream code rather than forced VALU usage

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