[AArch64] Severe AArch64DAGToDAGISel::Select build time regression on MSVC builds

[RKSimon]

The time taken to build AArch64ISelDAGToDAG.cpp on MSVC release builds has degraded severely over the past few months, with this now taking over 10mins to build on my normal dev machine.

This appears to be entirely due to the size of AArch64DAGToDAGISel::Select and the number of intrinsic expansions (in particular all the additional SME/SVE intrinsics) that are now performed, which appear to all being inlined.

The addition of a #pragma inline_depth(0) tag gets the build time to under 2 mins again, and could be an MSVC-only option, but I'd like to ask the aarch64 teams if there's any chance that we can move some of these intrinsics expansions into tablegen instead?

CC @CarolineConcatto @Lukacma @momchil-velikov @MDevereau

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Simon Pilgrim (RKSimon)

The time taken to build AArch64ISelDAGToDAG.cpp on MSVC release builds has degraded severely over the past few months, with this now taking over 10mins to build on my normal dev machine.

This appears to be entirely due to the size of AArch64DAGToDAGISel::Select and the number of intrinsic expansions (in particular all the additional SME/SVE intrinsics) that are now performed, which appear to all being inlined.

The addition of a #pragma inline_depth(0) tag gets the build time to under 2 mins again, and could be an MSVC-only option, but I'd like to ask the aarch64 teams if there's any chance that we can move some of these intrinsics expansions into tablegen instead?

CC @CarolineConcatto @Lukacma @momchil-velikov @MDevereau

[sdesmalen-arm]

Historically we added this code to AArch64DAGToDAGISel because TableGen patterns couldn't cope with multiple results. I'm not sure if anything has changed in TableGen to add such functionality, do you happen to know?

[tmatheson-arm]

Historically we added this code to AArch64DAGToDAGISel because TableGen patterns couldn't cope with multiple results. I'm not sure if anything has changed in TableGen to add such functionality, do you happen to know?

I had a WIP patch a while ago to implement multiple output patterns, but it didn't get much interest and I had to work on other things. AFAIK it is still a limitation.

[davemgreen]

We have patterns for MVE that produce multiple results, we get away with it either by not specifying the results type:

llvm-project/llvm/lib/Target/ARM/ARMInstrMVE.td

Line 1342 in 674574d

def : Pat<(ARMVMLALVs (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)),

Or by using set syntax:

llvm-project/llvm/lib/Target/ARM/ARMInstrMVE.td

Line 5695 in 674574d

[(set (VT MQPR:$Qd), (i32 tGPREven:$Rn),

[tmatheson-arm]

Ah sorry, what I was actually talking about is having multiple output instructions with no data dependency between them. IIRC we can have multiple output results, or even multiple instructions in the output pattern as long as the output from one depends on the other.