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[RISCV] vfslide1down+vmerge miscompile #106109

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@topperc

This test case

define <vscale x 4 x float> @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %false, float %1, <vscale x 4 x i1> %mask) nounwind {
                                                          
entry:                                                                           
  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(<vscale x 4 x float> undef, <vscale x 4 x float> %0, float %1, i64 4)
  %b = call <vscale x 4 x float> @llvm.riscv.vmerge.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> %false, <vscale x 4 x float> %a, <vscale x 4 x i1> %mask, i64 1)
  ret <vscale x 4 x float> %b                                                    
}

is compiled to

intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32: # @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32
# %bb.0:                                # %entry
        vsetivli        zero, 1, e32, m2, ta, mu
        vfslide1down.vf v10, v8, fa0, v0.t
        vmv.v.v v8, v10
        ret

The vfslide1down's VL was changed from 4 to 1. This causes fa0 to be inserted into element 0 instead of element 3.

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