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[HLSL] Update DXIL/SPIRV hybrid CodeGen tests to use a temp variable representing interchange target #105710

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@pow2clk

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@pow2clk

@farzonl suggested creating this issue to update some existing hybrid tests to leverage the regexp variables in filecheck to minimize duplication of CHECK lines.

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// Capture the expected interchange format so not every check needs to be duplicated
// DXCHECK: %hlsl.dot = call i32 @llvm.[[ICF:dx]].sdot.v2i32(<2 x i32>
// SPVCHECK: %hlsl.dot = call i32 @llvm.[[ICF:spv]].sdot.v2i32(<2 x i32>
// CHECK: ret i32 %hlsl.dot
int test_dot_int2(int2 p0, int2 p1) { return dot(p0, p1); }
// CHECK: %hlsl.dot = call i32 @llvm.[[ICF]].sdot.v3i32(<3 x i32>
// CHECK: ret i32 %hlsl.dot
int test_dot_int3(int3 p0, int3 p1) { return dot(p0, p1); }

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HLSLHLSL Language Supportclang:codegenIR generation bugs: mangling, exceptions, etc.good first issuehttps://github.com/llvm/llvm-project/contributetest-suite

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