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[AArch64][CodeGen] Fix wrong operand order when creating vcmla intrinsic
1 parent ee31ba0 commit b910732

11 files changed

+190
-190
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26216,7 +26216,7 @@ Value *AArch64TargetLowering::createComplexDeinterleavingIR(
2621626216

2621726217

2621826218
return B.CreateIntrinsic(IdMap[(int)Rotation], Ty,
26219-
{Accumulator, InputB, InputA});
26219+
{Accumulator, InputA, InputB});
2622026220
}
2622126221

2622226222
if (OperationType == ComplexDeinterleavingOperation::CAdd) {

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -48,14 +48,14 @@ define <4 x double> @mul_add_mull(<4 x double> %a, <4 x double> %b, <4 x double>
4848
; CHECK-NEXT: movi v17.2d, #0000000000000000
4949
; CHECK-NEXT: movi v18.2d, #0000000000000000
5050
; CHECK-NEXT: movi v19.2d, #0000000000000000
51-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v2.2d, #0
52-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v3.2d, #0
53-
; CHECK-NEXT: fcmla v17.2d, v5.2d, v7.2d, #0
54-
; CHECK-NEXT: fcmla v19.2d, v4.2d, v6.2d, #0
55-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v2.2d, #90
56-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v3.2d, #90
57-
; CHECK-NEXT: fcmla v17.2d, v5.2d, v7.2d, #90
58-
; CHECK-NEXT: fcmla v19.2d, v4.2d, v6.2d, #90
51+
; CHECK-NEXT: fcmla v16.2d, v2.2d, v0.2d, #0
52+
; CHECK-NEXT: fcmla v18.2d, v3.2d, v1.2d, #0
53+
; CHECK-NEXT: fcmla v17.2d, v7.2d, v5.2d, #0
54+
; CHECK-NEXT: fcmla v19.2d, v6.2d, v4.2d, #0
55+
; CHECK-NEXT: fcmla v16.2d, v2.2d, v0.2d, #90
56+
; CHECK-NEXT: fcmla v18.2d, v3.2d, v1.2d, #90
57+
; CHECK-NEXT: fcmla v17.2d, v7.2d, v5.2d, #90
58+
; CHECK-NEXT: fcmla v19.2d, v6.2d, v4.2d, #90
5959
; CHECK-NEXT: fadd v1.2d, v18.2d, v17.2d
6060
; CHECK-NEXT: fadd v0.2d, v16.2d, v19.2d
6161
; CHECK-NEXT: ret
@@ -94,14 +94,14 @@ define <4 x double> @mul_sub_mull(<4 x double> %a, <4 x double> %b, <4 x double>
9494
; CHECK-NEXT: movi v17.2d, #0000000000000000
9595
; CHECK-NEXT: movi v18.2d, #0000000000000000
9696
; CHECK-NEXT: movi v19.2d, #0000000000000000
97-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v2.2d, #0
98-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v3.2d, #0
99-
; CHECK-NEXT: fcmla v17.2d, v5.2d, v7.2d, #0
100-
; CHECK-NEXT: fcmla v19.2d, v4.2d, v6.2d, #0
101-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v2.2d, #90
102-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v3.2d, #90
103-
; CHECK-NEXT: fcmla v17.2d, v5.2d, v7.2d, #90
104-
; CHECK-NEXT: fcmla v19.2d, v4.2d, v6.2d, #90
97+
; CHECK-NEXT: fcmla v16.2d, v2.2d, v0.2d, #0
98+
; CHECK-NEXT: fcmla v18.2d, v3.2d, v1.2d, #0
99+
; CHECK-NEXT: fcmla v17.2d, v7.2d, v5.2d, #0
100+
; CHECK-NEXT: fcmla v19.2d, v6.2d, v4.2d, #0
101+
; CHECK-NEXT: fcmla v16.2d, v2.2d, v0.2d, #90
102+
; CHECK-NEXT: fcmla v18.2d, v3.2d, v1.2d, #90
103+
; CHECK-NEXT: fcmla v17.2d, v7.2d, v5.2d, #90
104+
; CHECK-NEXT: fcmla v19.2d, v6.2d, v4.2d, #90
105105
; CHECK-NEXT: fsub v1.2d, v18.2d, v17.2d
106106
; CHECK-NEXT: fsub v0.2d, v16.2d, v19.2d
107107
; CHECK-NEXT: ret
@@ -140,14 +140,14 @@ define <4 x double> @mul_conj_mull(<4 x double> %a, <4 x double> %b, <4 x double
140140
; CHECK-NEXT: movi v17.2d, #0000000000000000
141141
; CHECK-NEXT: movi v18.2d, #0000000000000000
142142
; CHECK-NEXT: movi v19.2d, #0000000000000000
143-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v2.2d, #0
144-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v3.2d, #0
145-
; CHECK-NEXT: fcmla v17.2d, v7.2d, v5.2d, #0
146-
; CHECK-NEXT: fcmla v19.2d, v6.2d, v4.2d, #0
147-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v2.2d, #90
148-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v3.2d, #90
149-
; CHECK-NEXT: fcmla v17.2d, v7.2d, v5.2d, #270
150-
; CHECK-NEXT: fcmla v19.2d, v6.2d, v4.2d, #270
143+
; CHECK-NEXT: fcmla v16.2d, v2.2d, v0.2d, #0
144+
; CHECK-NEXT: fcmla v18.2d, v3.2d, v1.2d, #0
145+
; CHECK-NEXT: fcmla v17.2d, v5.2d, v7.2d, #0
146+
; CHECK-NEXT: fcmla v19.2d, v4.2d, v6.2d, #0
147+
; CHECK-NEXT: fcmla v16.2d, v2.2d, v0.2d, #90
148+
; CHECK-NEXT: fcmla v18.2d, v3.2d, v1.2d, #90
149+
; CHECK-NEXT: fcmla v17.2d, v5.2d, v7.2d, #270
150+
; CHECK-NEXT: fcmla v19.2d, v4.2d, v6.2d, #270
151151
; CHECK-NEXT: fadd v1.2d, v18.2d, v17.2d
152152
; CHECK-NEXT: fadd v0.2d, v16.2d, v19.2d
153153
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,10 @@ target triple = "aarch64"
77
define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
88
; CHECK-LABEL: mull_add:
99
; CHECK: // %bb.0: // %entry
10-
; CHECK-NEXT: fcmla v4.2d, v2.2d, v0.2d, #0
11-
; CHECK-NEXT: fcmla v5.2d, v3.2d, v1.2d, #0
12-
; CHECK-NEXT: fcmla v4.2d, v2.2d, v0.2d, #90
13-
; CHECK-NEXT: fcmla v5.2d, v3.2d, v1.2d, #90
10+
; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #0
11+
; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #0
12+
; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #90
13+
; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #90
1414
; CHECK-NEXT: mov v0.16b, v4.16b
1515
; CHECK-NEXT: mov v1.16b, v5.16b
1616
; CHECK-NEXT: ret
@@ -39,14 +39,14 @@ define <4 x double> @mul_add_mull(<4 x double> %a, <4 x double> %b, <4 x double>
3939
; CHECK: // %bb.0: // %entry
4040
; CHECK-NEXT: movi v16.2d, #0000000000000000
4141
; CHECK-NEXT: movi v17.2d, #0000000000000000
42-
; CHECK-NEXT: fcmla v17.2d, v4.2d, v6.2d, #0
43-
; CHECK-NEXT: fcmla v16.2d, v5.2d, v7.2d, #0
44-
; CHECK-NEXT: fcmla v17.2d, v2.2d, v0.2d, #0
45-
; CHECK-NEXT: fcmla v16.2d, v3.2d, v1.2d, #0
46-
; CHECK-NEXT: fcmla v17.2d, v4.2d, v6.2d, #90
47-
; CHECK-NEXT: fcmla v16.2d, v5.2d, v7.2d, #90
48-
; CHECK-NEXT: fcmla v17.2d, v2.2d, v0.2d, #90
49-
; CHECK-NEXT: fcmla v16.2d, v3.2d, v1.2d, #90
42+
; CHECK-NEXT: fcmla v17.2d, v6.2d, v4.2d, #0
43+
; CHECK-NEXT: fcmla v16.2d, v7.2d, v5.2d, #0
44+
; CHECK-NEXT: fcmla v17.2d, v0.2d, v2.2d, #0
45+
; CHECK-NEXT: fcmla v16.2d, v1.2d, v3.2d, #0
46+
; CHECK-NEXT: fcmla v17.2d, v6.2d, v4.2d, #90
47+
; CHECK-NEXT: fcmla v16.2d, v7.2d, v5.2d, #90
48+
; CHECK-NEXT: fcmla v17.2d, v0.2d, v2.2d, #90
49+
; CHECK-NEXT: fcmla v16.2d, v1.2d, v3.2d, #90
5050
; CHECK-NEXT: mov v0.16b, v17.16b
5151
; CHECK-NEXT: mov v1.16b, v16.16b
5252
; CHECK-NEXT: ret
@@ -83,14 +83,14 @@ define <4 x double> @mul_sub_mull(<4 x double> %a, <4 x double> %b, <4 x double>
8383
; CHECK: // %bb.0: // %entry
8484
; CHECK-NEXT: movi v16.2d, #0000000000000000
8585
; CHECK-NEXT: movi v17.2d, #0000000000000000
86-
; CHECK-NEXT: fcmla v17.2d, v4.2d, v6.2d, #270
87-
; CHECK-NEXT: fcmla v16.2d, v5.2d, v7.2d, #270
88-
; CHECK-NEXT: fcmla v17.2d, v2.2d, v0.2d, #0
89-
; CHECK-NEXT: fcmla v16.2d, v3.2d, v1.2d, #0
90-
; CHECK-NEXT: fcmla v17.2d, v4.2d, v6.2d, #180
91-
; CHECK-NEXT: fcmla v16.2d, v5.2d, v7.2d, #180
92-
; CHECK-NEXT: fcmla v17.2d, v2.2d, v0.2d, #90
93-
; CHECK-NEXT: fcmla v16.2d, v3.2d, v1.2d, #90
86+
; CHECK-NEXT: fcmla v17.2d, v6.2d, v4.2d, #270
87+
; CHECK-NEXT: fcmla v16.2d, v7.2d, v5.2d, #270
88+
; CHECK-NEXT: fcmla v17.2d, v0.2d, v2.2d, #0
89+
; CHECK-NEXT: fcmla v16.2d, v1.2d, v3.2d, #0
90+
; CHECK-NEXT: fcmla v17.2d, v6.2d, v4.2d, #180
91+
; CHECK-NEXT: fcmla v16.2d, v7.2d, v5.2d, #180
92+
; CHECK-NEXT: fcmla v17.2d, v0.2d, v2.2d, #90
93+
; CHECK-NEXT: fcmla v16.2d, v1.2d, v3.2d, #90
9494
; CHECK-NEXT: mov v0.16b, v17.16b
9595
; CHECK-NEXT: mov v1.16b, v16.16b
9696
; CHECK-NEXT: ret
@@ -127,14 +127,14 @@ define <4 x double> @mul_conj_mull(<4 x double> %a, <4 x double> %b, <4 x double
127127
; CHECK: // %bb.0: // %entry
128128
; CHECK-NEXT: movi v16.2d, #0000000000000000
129129
; CHECK-NEXT: movi v17.2d, #0000000000000000
130-
; CHECK-NEXT: fcmla v17.2d, v2.2d, v0.2d, #0
131-
; CHECK-NEXT: fcmla v16.2d, v3.2d, v1.2d, #0
132-
; CHECK-NEXT: fcmla v17.2d, v2.2d, v0.2d, #90
133-
; CHECK-NEXT: fcmla v16.2d, v3.2d, v1.2d, #90
134-
; CHECK-NEXT: fcmla v17.2d, v6.2d, v4.2d, #0
135-
; CHECK-NEXT: fcmla v16.2d, v7.2d, v5.2d, #0
136-
; CHECK-NEXT: fcmla v17.2d, v6.2d, v4.2d, #270
137-
; CHECK-NEXT: fcmla v16.2d, v7.2d, v5.2d, #270
130+
; CHECK-NEXT: fcmla v17.2d, v0.2d, v2.2d, #0
131+
; CHECK-NEXT: fcmla v16.2d, v1.2d, v3.2d, #0
132+
; CHECK-NEXT: fcmla v17.2d, v0.2d, v2.2d, #90
133+
; CHECK-NEXT: fcmla v16.2d, v1.2d, v3.2d, #90
134+
; CHECK-NEXT: fcmla v17.2d, v4.2d, v6.2d, #0
135+
; CHECK-NEXT: fcmla v16.2d, v5.2d, v7.2d, #0
136+
; CHECK-NEXT: fcmla v17.2d, v4.2d, v6.2d, #270
137+
; CHECK-NEXT: fcmla v16.2d, v5.2d, v7.2d, #270
138138
; CHECK-NEXT: mov v0.16b, v17.16b
139139
; CHECK-NEXT: mov v1.16b, v16.16b
140140
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,8 @@ define <4 x half> @complex_mul_v4f16(<4 x half> %a, <4 x half> %b) {
3737
; CHECK-LABEL: complex_mul_v4f16:
3838
; CHECK: // %bb.0: // %entry
3939
; CHECK-NEXT: movi d2, #0000000000000000
40-
; CHECK-NEXT: fcmla v2.4h, v0.4h, v1.4h, #0
41-
; CHECK-NEXT: fcmla v2.4h, v0.4h, v1.4h, #90
40+
; CHECK-NEXT: fcmla v2.4h, v1.4h, v0.4h, #0
41+
; CHECK-NEXT: fcmla v2.4h, v1.4h, v0.4h, #90
4242
; CHECK-NEXT: fmov d0, d2
4343
; CHECK-NEXT: ret
4444
entry:
@@ -61,8 +61,8 @@ define <8 x half> @complex_mul_v8f16(<8 x half> %a, <8 x half> %b) {
6161
; CHECK-LABEL: complex_mul_v8f16:
6262
; CHECK: // %bb.0: // %entry
6363
; CHECK-NEXT: movi v2.2d, #0000000000000000
64-
; CHECK-NEXT: fcmla v2.8h, v0.8h, v1.8h, #0
65-
; CHECK-NEXT: fcmla v2.8h, v0.8h, v1.8h, #90
64+
; CHECK-NEXT: fcmla v2.8h, v1.8h, v0.8h, #0
65+
; CHECK-NEXT: fcmla v2.8h, v1.8h, v0.8h, #90
6666
; CHECK-NEXT: mov v0.16b, v2.16b
6767
; CHECK-NEXT: ret
6868
entry:
@@ -86,10 +86,10 @@ define <16 x half> @complex_mul_v16f16(<16 x half> %a, <16 x half> %b) {
8686
; CHECK: // %bb.0: // %entry
8787
; CHECK-NEXT: movi v4.2d, #0000000000000000
8888
; CHECK-NEXT: movi v5.2d, #0000000000000000
89-
; CHECK-NEXT: fcmla v5.8h, v0.8h, v2.8h, #0
90-
; CHECK-NEXT: fcmla v4.8h, v1.8h, v3.8h, #0
91-
; CHECK-NEXT: fcmla v5.8h, v0.8h, v2.8h, #90
92-
; CHECK-NEXT: fcmla v4.8h, v1.8h, v3.8h, #90
89+
; CHECK-NEXT: fcmla v5.8h, v2.8h, v0.8h, #0
90+
; CHECK-NEXT: fcmla v4.8h, v3.8h, v1.8h, #0
91+
; CHECK-NEXT: fcmla v5.8h, v2.8h, v0.8h, #90
92+
; CHECK-NEXT: fcmla v4.8h, v3.8h, v1.8h, #90
9393
; CHECK-NEXT: mov v0.16b, v5.16b
9494
; CHECK-NEXT: mov v1.16b, v4.16b
9595
; CHECK-NEXT: ret
@@ -116,14 +116,14 @@ define <32 x half> @complex_mul_v32f16(<32 x half> %a, <32 x half> %b) {
116116
; CHECK-NEXT: movi v17.2d, #0000000000000000
117117
; CHECK-NEXT: movi v18.2d, #0000000000000000
118118
; CHECK-NEXT: movi v19.2d, #0000000000000000
119-
; CHECK-NEXT: fcmla v16.8h, v0.8h, v4.8h, #0
120-
; CHECK-NEXT: fcmla v18.8h, v1.8h, v5.8h, #0
121-
; CHECK-NEXT: fcmla v17.8h, v3.8h, v7.8h, #0
122-
; CHECK-NEXT: fcmla v19.8h, v2.8h, v6.8h, #0
123-
; CHECK-NEXT: fcmla v16.8h, v0.8h, v4.8h, #90
124-
; CHECK-NEXT: fcmla v18.8h, v1.8h, v5.8h, #90
125-
; CHECK-NEXT: fcmla v17.8h, v3.8h, v7.8h, #90
126-
; CHECK-NEXT: fcmla v19.8h, v2.8h, v6.8h, #90
119+
; CHECK-NEXT: fcmla v16.8h, v4.8h, v0.8h, #0
120+
; CHECK-NEXT: fcmla v18.8h, v5.8h, v1.8h, #0
121+
; CHECK-NEXT: fcmla v17.8h, v7.8h, v3.8h, #0
122+
; CHECK-NEXT: fcmla v19.8h, v6.8h, v2.8h, #0
123+
; CHECK-NEXT: fcmla v16.8h, v4.8h, v0.8h, #90
124+
; CHECK-NEXT: fcmla v18.8h, v5.8h, v1.8h, #90
125+
; CHECK-NEXT: fcmla v17.8h, v7.8h, v3.8h, #90
126+
; CHECK-NEXT: fcmla v19.8h, v6.8h, v2.8h, #90
127127
; CHECK-NEXT: mov v0.16b, v16.16b
128128
; CHECK-NEXT: mov v1.16b, v18.16b
129129
; CHECK-NEXT: mov v3.16b, v17.16b

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ define <2 x float> @complex_mul_v2f32(<2 x float> %a, <2 x float> %b) {
88
; CHECK-LABEL: complex_mul_v2f32:
99
; CHECK: // %bb.0: // %entry
1010
; CHECK-NEXT: movi d2, #0000000000000000
11-
; CHECK-NEXT: fcmla v2.2s, v0.2s, v1.2s, #0
12-
; CHECK-NEXT: fcmla v2.2s, v0.2s, v1.2s, #90
11+
; CHECK-NEXT: fcmla v2.2s, v1.2s, v0.2s, #0
12+
; CHECK-NEXT: fcmla v2.2s, v1.2s, v0.2s, #90
1313
; CHECK-NEXT: fmov d0, d2
1414
; CHECK-NEXT: ret
1515
entry:
@@ -32,8 +32,8 @@ define <4 x float> @complex_mul_v4f32(<4 x float> %a, <4 x float> %b) {
3232
; CHECK-LABEL: complex_mul_v4f32:
3333
; CHECK: // %bb.0: // %entry
3434
; CHECK-NEXT: movi v2.2d, #0000000000000000
35-
; CHECK-NEXT: fcmla v2.4s, v0.4s, v1.4s, #0
36-
; CHECK-NEXT: fcmla v2.4s, v0.4s, v1.4s, #90
35+
; CHECK-NEXT: fcmla v2.4s, v1.4s, v0.4s, #0
36+
; CHECK-NEXT: fcmla v2.4s, v1.4s, v0.4s, #90
3737
; CHECK-NEXT: mov v0.16b, v2.16b
3838
; CHECK-NEXT: ret
3939
entry:
@@ -57,10 +57,10 @@ define <8 x float> @complex_mul_v8f32(<8 x float> %a, <8 x float> %b) {
5757
; CHECK: // %bb.0: // %entry
5858
; CHECK-NEXT: movi v4.2d, #0000000000000000
5959
; CHECK-NEXT: movi v5.2d, #0000000000000000
60-
; CHECK-NEXT: fcmla v5.4s, v0.4s, v2.4s, #0
61-
; CHECK-NEXT: fcmla v4.4s, v1.4s, v3.4s, #0
62-
; CHECK-NEXT: fcmla v5.4s, v0.4s, v2.4s, #90
63-
; CHECK-NEXT: fcmla v4.4s, v1.4s, v3.4s, #90
60+
; CHECK-NEXT: fcmla v5.4s, v2.4s, v0.4s, #0
61+
; CHECK-NEXT: fcmla v4.4s, v3.4s, v1.4s, #0
62+
; CHECK-NEXT: fcmla v5.4s, v2.4s, v0.4s, #90
63+
; CHECK-NEXT: fcmla v4.4s, v3.4s, v1.4s, #90
6464
; CHECK-NEXT: mov v0.16b, v5.16b
6565
; CHECK-NEXT: mov v1.16b, v4.16b
6666
; CHECK-NEXT: ret
@@ -87,14 +87,14 @@ define <16 x float> @complex_mul_v16f32(<16 x float> %a, <16 x float> %b) {
8787
; CHECK-NEXT: movi v17.2d, #0000000000000000
8888
; CHECK-NEXT: movi v18.2d, #0000000000000000
8989
; CHECK-NEXT: movi v19.2d, #0000000000000000
90-
; CHECK-NEXT: fcmla v16.4s, v0.4s, v4.4s, #0
91-
; CHECK-NEXT: fcmla v18.4s, v1.4s, v5.4s, #0
92-
; CHECK-NEXT: fcmla v17.4s, v3.4s, v7.4s, #0
93-
; CHECK-NEXT: fcmla v19.4s, v2.4s, v6.4s, #0
94-
; CHECK-NEXT: fcmla v16.4s, v0.4s, v4.4s, #90
95-
; CHECK-NEXT: fcmla v18.4s, v1.4s, v5.4s, #90
96-
; CHECK-NEXT: fcmla v17.4s, v3.4s, v7.4s, #90
97-
; CHECK-NEXT: fcmla v19.4s, v2.4s, v6.4s, #90
90+
; CHECK-NEXT: fcmla v16.4s, v4.4s, v0.4s, #0
91+
; CHECK-NEXT: fcmla v18.4s, v5.4s, v1.4s, #0
92+
; CHECK-NEXT: fcmla v17.4s, v7.4s, v3.4s, #0
93+
; CHECK-NEXT: fcmla v19.4s, v6.4s, v2.4s, #0
94+
; CHECK-NEXT: fcmla v16.4s, v4.4s, v0.4s, #90
95+
; CHECK-NEXT: fcmla v18.4s, v5.4s, v1.4s, #90
96+
; CHECK-NEXT: fcmla v17.4s, v7.4s, v3.4s, #90
97+
; CHECK-NEXT: fcmla v19.4s, v6.4s, v2.4s, #90
9898
; CHECK-NEXT: mov v0.16b, v16.16b
9999
; CHECK-NEXT: mov v1.16b, v18.16b
100100
; CHECK-NEXT: mov v3.16b, v17.16b

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ define <2 x double> @complex_mul_v2f64(<2 x double> %a, <2 x double> %b) {
88
; CHECK-LABEL: complex_mul_v2f64:
99
; CHECK: // %bb.0: // %entry
1010
; CHECK-NEXT: movi v2.2d, #0000000000000000
11-
; CHECK-NEXT: fcmla v2.2d, v0.2d, v1.2d, #0
12-
; CHECK-NEXT: fcmla v2.2d, v0.2d, v1.2d, #90
11+
; CHECK-NEXT: fcmla v2.2d, v1.2d, v0.2d, #0
12+
; CHECK-NEXT: fcmla v2.2d, v1.2d, v0.2d, #90
1313
; CHECK-NEXT: mov v0.16b, v2.16b
1414
; CHECK-NEXT: ret
1515
entry:
@@ -33,10 +33,10 @@ define <4 x double> @complex_mul_v4f64(<4 x double> %a, <4 x double> %b) {
3333
; CHECK: // %bb.0: // %entry
3434
; CHECK-NEXT: movi v4.2d, #0000000000000000
3535
; CHECK-NEXT: movi v5.2d, #0000000000000000
36-
; CHECK-NEXT: fcmla v5.2d, v0.2d, v2.2d, #0
37-
; CHECK-NEXT: fcmla v4.2d, v1.2d, v3.2d, #0
38-
; CHECK-NEXT: fcmla v5.2d, v0.2d, v2.2d, #90
39-
; CHECK-NEXT: fcmla v4.2d, v1.2d, v3.2d, #90
36+
; CHECK-NEXT: fcmla v5.2d, v2.2d, v0.2d, #0
37+
; CHECK-NEXT: fcmla v4.2d, v3.2d, v1.2d, #0
38+
; CHECK-NEXT: fcmla v5.2d, v2.2d, v0.2d, #90
39+
; CHECK-NEXT: fcmla v4.2d, v3.2d, v1.2d, #90
4040
; CHECK-NEXT: mov v0.16b, v5.16b
4141
; CHECK-NEXT: mov v1.16b, v4.16b
4242
; CHECK-NEXT: ret
@@ -63,14 +63,14 @@ define <8 x double> @complex_mul_v8f64(<8 x double> %a, <8 x double> %b) {
6363
; CHECK-NEXT: movi v17.2d, #0000000000000000
6464
; CHECK-NEXT: movi v18.2d, #0000000000000000
6565
; CHECK-NEXT: movi v19.2d, #0000000000000000
66-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v4.2d, #0
67-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v5.2d, #0
68-
; CHECK-NEXT: fcmla v17.2d, v3.2d, v7.2d, #0
69-
; CHECK-NEXT: fcmla v19.2d, v2.2d, v6.2d, #0
70-
; CHECK-NEXT: fcmla v16.2d, v0.2d, v4.2d, #90
71-
; CHECK-NEXT: fcmla v18.2d, v1.2d, v5.2d, #90
72-
; CHECK-NEXT: fcmla v17.2d, v3.2d, v7.2d, #90
73-
; CHECK-NEXT: fcmla v19.2d, v2.2d, v6.2d, #90
66+
; CHECK-NEXT: fcmla v16.2d, v4.2d, v0.2d, #0
67+
; CHECK-NEXT: fcmla v18.2d, v5.2d, v1.2d, #0
68+
; CHECK-NEXT: fcmla v17.2d, v7.2d, v3.2d, #0
69+
; CHECK-NEXT: fcmla v19.2d, v6.2d, v2.2d, #0
70+
; CHECK-NEXT: fcmla v16.2d, v4.2d, v0.2d, #90
71+
; CHECK-NEXT: fcmla v18.2d, v5.2d, v1.2d, #90
72+
; CHECK-NEXT: fcmla v17.2d, v7.2d, v3.2d, #90
73+
; CHECK-NEXT: fcmla v19.2d, v6.2d, v2.2d, #90
7474
; CHECK-NEXT: mov v0.16b, v16.16b
7575
; CHECK-NEXT: mov v1.16b, v18.16b
7676
; CHECK-NEXT: mov v3.16b, v17.16b

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