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I introduced an interface for hardware contracts to the verif dialect. This should be exposed to FIRRTL so that we can access it via Chisel. Here is an idea of what is needed:
Modules need to be able to contain a contract region that contains the module's pre-post-conditions (as well as future invariants that might be introduces). This can also contain arbitrary hardware and reason about the module's interface. This should map to verif.contract.
We need a way to define preconditions, probably through something like require, that maps to verif.require.
We need a way to define postconditions, with something like ensure, that maps to verif.ensure. These should be allowed to reason about the module's outputs.
Here's an example of how I think this can be used:
public moduleFoo:
inputin : UInt<32>outputout : UInt<32>
contract:
nodeprec0 = gt(in, 0)
require prec0
nodeprec1 = lt(in, 1000)
require prec1
nodepost = ;;some post-condition;;
ensure post
;; Body of the module
The text was updated successfully, but these errors were encountered:
Hey @dobios, I'm definitely going to poke at this in the near future! This is a fantastic building block to make formal verification more modular and composable.
I introduced an interface for hardware contracts to the
verif
dialect. This should be exposed to FIRRTL so that we can access it via Chisel. Here is an idea of what is needed:contract
region that contains the module's pre-post-conditions (as well as future invariants that might be introduces). This can also contain arbitrary hardware and reason about the module's interface. This should map toverif.contract
.require
, that maps toverif.require
.ensure
, that maps toverif.ensure
. These should be allowed to reason about the module's outputs.Here's an example of how I think this can be used:
The text was updated successfully, but these errors were encountered: