[FIRRTL] lowering-options=disallowPackedArrays not erroring properly

[abejgonzalez]

According to

circt/docs/VerilogGeneration.md

Line 83 in c17842c

* `disallowPackedArrays` (default=`false`). If true, eliminate packed arrays

, disallowPackedArrays should remove packed arrays from the Verilog output. However, I am not seeing this happen in my Chipyard-based design. Here is a test case that I created:

Test test.fir:

circuit Foo:
  module Foo:
    input clock: Clock
    input idx: UInt<2>
 
    wire t : UInt<3>[8]
    t[0] <= UInt<1>("h0")
    t[1] <= UInt<1>("h0")
    t[2] <= UInt<1>("h1")
    t[3] <= UInt<1>("h1")
    t[4] <= UInt<1>("h1")
    t[5] <= UInt<2>("h2")
    t[6] <= UInt<3>("h5")
    t[7] <= UInt<3>("h4")

    node _T = eq(idx, t[idx])

    printf(clock, _T, "")

Test Cmdline:

firtool --lowering-options=disallowPackedArrays --preserve-values-all=all test.fir

Test Output w/o disallowPackedArrays:

+ firtool --preserve-values=all test.fir
// Generated by CIRCT unknown git version
// Standard header to adapt well known macros to our needs.

// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifdef PRINTF_COND
  `define PRINTF_COND_ (`PRINTF_COND)
`else  // PRINTF_COND
  `define PRINTF_COND_ 1
`endif // PRINTF_COND

module Foo(
  input       clock,
  input [1:0] idx);

  wire [7:0][2:0] _GEN = '{3'h4, 3'h5, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
  wire [2:0]      t_0 = 3'h0;
  wire [2:0]      t_1 = 3'h0;
  wire [2:0]      t_2 = 3'h1;
  wire [2:0]      t_3 = 3'h1;
  wire [2:0]      t_4 = 3'h1;
  wire [2:0]      t_5 = 3'h2;
  wire [2:0]      t_6 = 3'h5;
  wire [2:0]      t_7 = 3'h4;
  wire [2:0]      _GEN_0 = {1'h0, idx};
  wire [2:0]      _GEN_1;
  /* synopsys infer_mux_override */
  assign _GEN_1 = _GEN[_GEN_0] /* cadence map_to_mux */;
  wire            _T = _GEN_0 == _GEN_1;
  `ifndef SYNTHESIS
    always @(posedge clock) begin
      if ((`PRINTF_COND_) & _T)
        $fwrite(32'h80000002, "");
    end // always @(posedge)
  `endif // not def SYNTHESIS
endmodule

Test Output w/ disallowPackedArrays:

+ firtool --lowering-options=disallowPackedArrays --preserve-values=all test.fir
test.fir:16:25: error: unsupported packed array expression
    node _T = eq(idx, t[idx])
                        ^
test.fir:16:25: note: see current operation: %0 = "hw.aggregate_constant"() {fields = [-4 : i3, -3 : i3, 2 : i3, 1 : i3, 1 : i3, 1 : i3, 0 : i3, 0 : i3]} : () -> !hw.array<8xi3>
// Generated by CIRCT unknown git version
// Standard header to adapt well known macros to our needs.

// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifdef PRINTF_COND
  `define PRINTF_COND_ (`PRINTF_COND)
`else  // PRINTF_COND
  `define PRINTF_COND_ 1
`endif // PRINTF_COND

module Foo(
  input       clock,
  input [1:0] idx);

  wire [7:0][2:0] _GEN = '{3'h4, 3'h5, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
  wire [2:0]      t_0 = 3'h0;
  wire [2:0]      t_1 = 3'h0;
  wire [2:0]      t_2 = 3'h1;
  wire [2:0]      t_3 = 3'h1;
  wire [2:0]      t_4 = 3'h1;
  wire [2:0]      t_5 = 3'h2;
  wire [2:0]      t_6 = 3'h5;
  wire [2:0]      t_7 = 3'h4;
  wire [2:0]      _GEN_0 = {1'h0, idx};
  wire [2:0]      _GEN_1;
  /* synopsys infer_mux_override */
  assign _GEN_1 = _GEN[_GEN_0] /* cadence map_to_mux */;
  wire            _T = _GEN_0 == _GEN_1;
  `ifndef SYNTHESIS
    always @(posedge clock) begin
      if ((`PRINTF_COND_) & _T)
        $fwrite(32'h80000002, "");
    end // always @(posedge)
  `endif // not def SYNTHESIS
endmodule

This seems suspect. If the flag is given, I would expect that there would be no error and the output Verilog with be formed correctly (no packed arrays). However, I see an error message, a 0 return code (i.e. success) and verilog output that has a packed array. Is this expected? Is the output Verilog supposed to be xformed?

This is part of the work on ucb-bar/chipyard#1324 when running CIRCT designs through Genus.

[uenoku]

Thank you for the report! #4626 should fix the issue.