Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[FIRRTL] Optimize analog-connect-lowering #4467

Open
tymcauley opened this issue Dec 20, 2022 · 1 comment
Open

[FIRRTL] Optimize analog-connect-lowering #4467

tymcauley opened this issue Dec 20, 2022 · 1 comment

Comments

@tymcauley
Copy link
Contributor

In #4466, I introduced a workaround to resolve #4112, which removes some unnecessary alias/assign code when connecting module instances with analog wires. However, as noted in the PR comments, the fix isn't quite ideal since it doesn't avoid generating some wires. Those wires get removed by DCE, but ideally they wouldn't exist in the first place.

If those wires were removed, then we could make the test code introduced in that same PR a bit nicer: it could be written as all CHECK-NEXT statements, since those temporary wires wouldn't be polluting the lower-firrtl-to-hw output.

@uenoku
Copy link
Member

uenoku commented Dec 21, 2022

Maybe we can port the optimizations implemented in LowerToHW to normal canonicalizers?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants