@@ -104,8 +104,7 @@ hw.module.generated @FIRRTLMem_1_1_1_16_10_0_1_0_0, @FIRRTLMem(in %ro_addr_0: i4
104104//CHECK-NEXT: %[[rwdata2:.+]] = comb.mux %[[rwrcond]], %[[rwdata]], %[[x2]]
105105//CHECK-NEXT: sv.assign %[[rwtmp]], %[[rwdata2:.+]]
106106//CHECK-NEXT: sv.always posedge %rw_clock_0 {
107- //CHECK-NEXT: %[[rwwcondpre:.+]] = comb.and %rw_wmode_0, %true
108- //CHECK-NEXT: %[[rwwcond:.+]] = comb.and %rw_en_0, %[[rwwcondpre]]
107+ //CHECK-NEXT: %[[rwwcond:.+]] = comb.and %rw_en_0, %rw_wmode_0
109108//CHECK-NEXT: sv.if %[[rwwcond]] {
110109//CHECK-NEXT: %[[rwwslot:.+]] = sv.array_index_inout %Memory[%rw_addr_0]
111110//CHECK-NEXT: %[[c0_i32:.+]] = hw.constant 0 : i32
@@ -393,8 +392,7 @@ hw.module.generated @ReadWriteWithHighReadLatency, @FIRRTLMem(in %rw_addr: i4, i
393392
394393// Write port
395394// CHECK: sv.always
396- // CHECK: [[TMP:%.+]] = comb.and [[WMODE_1R]], %true
397- // CHECK: [[WCOND:%.+]] comb.and [[EN_1R]], [[TMP]]
395+ // CHECK: [[WCOND:%.+]] comb.and [[EN_1R]], [[WMODE_1R]]
398396// CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[ADDR_1R]]]
399397
400398// COMMON-LABEL: hw.module private @ReadWriteWithHighWriteLatency
@@ -442,8 +440,7 @@ hw.module.generated @ReadWriteWithHighWriteLatency, @FIRRTLMem(in %rw_addr: i4,
442440
443441// Write port
444442// CHECK: sv.always
445- // CHECK: [[TMP:%.+]] = comb.and [[WRITE_WMODE_3R]], %true
446- // CHECK: [[WCOND:%.+]] comb.and [[WRITE_EN_3R]], [[TMP]]
443+ // CHECK: [[WCOND:%.+]] comb.and [[WRITE_EN_3R]], [[WRITE_WMODE_3R]]
447444// CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[WRITE_ADDR_3R]]]
448445
449446emit.fragment @Fragment {}
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