Skip to content
This repository has been archived by the owner on Apr 23, 2020. It is now read-only.

Fixed typo in BigEndianNEON.rst #18

Closed
wants to merge 1 commit into from
Closed

Fixed typo in BigEndianNEON.rst #18

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Fixed typo in BigEndianNEON.rst
  • Loading branch information
U-PITT\mpu2 authored and U-PITT\mpu2 committed Dec 4, 2015
commit 9fb040640a28c773761ebbebba825925a4ee13f4
2 changes: 1 addition & 1 deletion docs/BigEndianNEON.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ A vector is a consecutive sequence of items that are operated on simultaneously.

Because of this, the instruction ``LD1`` performs a vector load but performs byte swapping not on the entire 64 bits, but on the individual items within the vector. This means that the register content is the same as it would have been on a little endian system.

It may seem that ``LD1`` should suffice to peform vector loads on a big endian machine. However there are pros and cons to the two approaches that make it less than simple which register format to pick.
It may seem that ``LD1`` should suffice to perform vector loads on a big endian machine. However there are pros and cons to the two approaches that make it less than simple which register format to pick.

There are two options:

Expand Down