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  1. Zynq_SOC_7010_dev Zynq_SOC_7010_dev Public

    Zynq_SOC_7010_dev

    Tcl 2

  2. AXI_specs AXI_specs Public

    AXI Specification and Docs

  3. amaranth-soc amaranth-soc Public

    Forked from amaranth-lang/amaranth-soc

    System on Chip toolkit for Amaranth HDL

    Python

  4. axi axi Public

    Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog

  5. pulpissimo pulpissimo Public

    Forked from pulp-platform/pulpissimo

    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

    SystemVerilog

  6. Verification-of-Common-Peripherals-Memories-and-Bus-Protocol Verification-of-Common-Peripherals-Memories-and-Bus-Protocol Public

    Forked from sakshamssy/Verification-of-Common-Peripherals-Memories-and-Bus-Protocol

    Verification of Memories viz. FIFO Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone Verification of Interface Communication Protocols viz. SPI, UART, I2C Verification of Simple Compinati…

    SystemVerilog

livesteps · GitHub
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  1. Zynq_SOC_7010_dev Zynq_SOC_7010_dev Public

    Zynq_SOC_7010_dev

    Tcl 2

  2. AXI_specs AXI_specs Public

    AXI Specification and Docs

  3. amaranth-soc amaranth-soc Public

    Forked from amaranth-lang/amaranth-soc

    System on Chip toolkit for Amaranth HDL

    Python

  4. axi axi Public

    Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog

  5. pulpissimo pulpissimo Public

    Forked from pulp-platform/pulpissimo

    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

    SystemVerilog

  6. Verification-of-Common-Peripherals-Memories-and-Bus-Protocol Verification-of-Common-Peripherals-Memories-and-Bus-Protocol Public

    Forked from sakshamssy/Verification-of-Common-Peripherals-Memories-and-Bus-Protocol

    Verification of Memories viz. FIFO Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone Verification of Interface Communication Protocols viz. SPI, UART, I2C Verification of Simple Compinati…

    SystemVerilog

livesteps · GitHub
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Popular repositories Loading

  1. Zynq_SOC_7010_dev Zynq_SOC_7010_dev Public

    Zynq_SOC_7010_dev

    Tcl 2

  2. AXI_specs AXI_specs Public

    AXI Specification and Docs

  3. amaranth-soc amaranth-soc Public

    Forked from amaranth-lang/amaranth-soc

    System on Chip toolkit for Amaranth HDL

    Python

  4. axi axi Public

    Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog

  5. pulpissimo pulpissimo Public

    Forked from pulp-platform/pulpissimo

    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

    SystemVerilog

  6. Verification-of-Common-Peripherals-Memories-and-Bus-Protocol Verification-of-Common-Peripherals-Memories-and-Bus-Protocol Public

    Forked from sakshamssy/Verification-of-Common-Peripherals-Memories-and-Bus-Protocol

    Verification of Memories viz. FIFO Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone Verification of Interface Communication Protocols viz. SPI, UART, I2C Verification of Simple Compinati…

    SystemVerilog