arch: arm: soc: stm32l0: add I2C support

Add I2C support for STM32L0 series. LL-based driver was already in place, so I've just enable it. Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
lindblandro · Mar 14, 2018 · 9ae3fdc · 9ae3fdc
1 parent bb3e5d7
commit 9ae3fdc
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Showing 8 changed files with 122 additions and 5 deletions.
diff --git a/arch/arm/soc/st_stm32/stm32l0/Kconfig.defconfig.series b/arch/arm/soc/st_stm32/stm32l0/Kconfig.defconfig.series
@@ -16,5 +16,11 @@ if GPIO_STM32
 
 endif # GPIO_STM32
 
+if I2C && (I2C_1 || I2C_2 || I2C_3)
+
+config  I2C_STM32_V2
+	def_bool y
+
+endif # I2C
 
 endif # SOC_SERIES_STM32L0X
diff --git a/arch/arm/soc/st_stm32/stm32l0/dts.fixup b/arch/arm/soc/st_stm32/stm32l0/dts.fixup
@@ -14,4 +14,22 @@
 #define CONFIG_UART_STM32_PORT_2_NAME		ST_STM32_USART_40004400_LABEL
 #define PORT_2_IRQ				ST_STM32_USART_40004400_IRQ_0
 
+#define CONFIG_I2C_1_BASE_ADDRESS		ST_STM32_I2C_V2_40005400_BASE_ADDRESS
+#define CONFIG_I2C_1_COMBINED_IRQ_PRI		ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
+#define CONFIG_I2C_1_NAME			ST_STM32_I2C_V2_40005400_LABEL
+#define CONFIG_I2C_1_COMBINED_IRQ		ST_STM32_I2C_V2_40005400_IRQ_COMBINED
+#define CONFIG_I2C_1_BITRATE			ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_2_BASE_ADDRESS		ST_STM32_I2C_V2_40005800_BASE_ADDRESS
+#define CONFIG_I2C_2_COMBINED_IRQ_PRI		ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
+#define CONFIG_I2C_2_NAME			ST_STM32_I2C_V2_40005800_LABEL
+#define CONFIG_I2C_2_COMBINED_IRQ		ST_STM32_I2C_V2_40005800_IRQ_COMBINED
+#define CONFIG_I2C_2_BITRATE			ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_3_BASE_ADDRESS		ST_STM32_I2C_V2_40007800_BASE_ADDRESS
+#define CONFIG_I2C_3_COMBINED_IRQ_PRI		ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY
+#define CONFIG_I2C_3_NAME			ST_STM32_I2C_V2_40007800_LABEL
+#define CONFIG_I2C_3_COMBINED_IRQ		ST_STM32_I2C_V2_40007800_IRQ_COMBINED
+#define CONFIG_I2C_3_BITRATE			ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
+
 /* End of SoC Level DTS fixup file */
diff --git a/arch/arm/soc/st_stm32/stm32l0/soc.h b/arch/arm/soc/st_stm32/stm32l0/soc.h
@@ -42,6 +42,10 @@
 #include <stm32l0xx_ll_system.h>
 #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
+#ifdef CONFIG_I2C_STM32_V2
+#include <stm32l0xx_ll_i2c.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32L0_SOC_H_ */
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
@@ -100,16 +100,16 @@ config I2C_STM32_V1
 	  driver also supports the F2 and L1 series.
 
 config I2C_STM32_V2
-	bool "STM32 V2 Driver (F0/F3/L4X)"
+	bool "STM32 V2 Driver (F0/F3/L0/L4X)"
 	depends on SOC_FAMILY_STM32
-	depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X
+	depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
 	select HAS_DTS_I2C
 	select USE_STM32_LL_I2C
 	select USE_STM32_LL_RCC if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
 	default n
 	help
-	  Enable I2C support on the STM32 F0, F3 and L4X family of processors.
-	  This driver also supports the F7 and L0 series.
+	  Enable I2C support on the STM32 F0, F3, L0 and L4X family of processors.
+	  This driver also supports the F7 series.
 
 config I2C_STM32_INTERRUPT
 	bool "STM32 MCU I2C Interrupt Support"
@@ -121,7 +121,7 @@ config I2C_STM32_INTERRUPT
 config I2C_STM32_COMBINED_INTERRUPT
 	bool
 	depends on I2C_STM32_INTERRUPT
-	default y if SOC_SERIES_STM32F0X
+	default y if SOC_SERIES_STM32F0X || SOC_SERIES_STM32L0X
 
 config I2C_BITBANG
 	bool

diff --git a/drivers/pinmux/stm32/pinmux_stm32l0.h b/drivers/pinmux/stm32/pinmux_stm32l0.h
@@ -31,4 +31,24 @@
 #define STM32L0_PINMUX_FUNC_PA15_USART2_RX \
 	(STM32_PINMUX_ALT_FUNC_4 | STM32_PUPDR_NO_PULL)
 
+#define STM32L0_PINMUX_FUNC_PB8_I2C1_SCL \
+	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
+#define STM32L0_PINMUX_FUNC_PB9_I2C1_SDA \
+	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
+
+#define STM32L0_PINMUX_FUNC_PA9_I2C1_SCL \
+	(STM32_PINMUX_ALT_FUNC_6 | STM32_OPENDRAIN_PULLUP)
+#define STM32L0_PINMUX_FUNC_PA10_I2C1_SDA \
+	(STM32_PINMUX_ALT_FUNC_6 | STM32_OPENDRAIN_PULLUP)
+
+#define STM32L0_PINMUX_FUNC_PB13_I2C2_SCL \
+	(STM32_PINMUX_ALT_FUNC_5 | STM32_OPENDRAIN_PULLUP)
+#define STM32L0_PINMUX_FUNC_PB14_I2C2_SDA \
+	(STM32_PINMUX_ALT_FUNC_5 | STM32_OPENDRAIN_PULLUP)
+
+#define STM32L0_PINMUX_FUNC_PC0_I2C3_SCL \
+	(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
+#define STM32L0_PINMUX_FUNC_PC1_I2C3_SDA \
+	(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
+
 #endif /* _STM32L0_PINMUX_H_ */
diff --git a/dts/arm/st/stm32l0.dtsi b/dts/arm/st/stm32l0.dtsi
@@ -8,6 +8,7 @@
 #include <arm/armv6-m.dtsi>
 #include <st/mem.h>
 #include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
 
 / {
 	cpus {
@@ -78,6 +79,18 @@
 			status = "disabled";
 			label = "UART_2";
 		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			interrupts = <23 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_1";
+		};
 	};
 };
 

diff --git a/dts/arm/st/stm32l072.dtsi b/dts/arm/st/stm32l072.dtsi
@@ -5,3 +5,31 @@
  */
 
 #include <st/stm32l0.dtsi>
+
+/ {
+	soc {
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40007800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007800 0x400>;
+			interrupts = <21 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_3";
+		};
+	};
+};
diff --git a/dts/arm/st/stm32l073.dtsi b/dts/arm/st/stm32l073.dtsi
@@ -5,3 +5,31 @@
  */
 
 #include <st/stm32l0.dtsi>
+
+/ {
+	soc {
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40007800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007800 0x400>;
+			interrupts = <21 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_3";
+		};
+	};
+};