[iss] Prevent FP loads from speculative wakeups.

lihaokang · May 17, 2018 · 3b97569 · 3b97569
1 parent b9b7d1f
commit 3b97569
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -637,7 +637,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    val mem_iq = issue_units.find(_.iqType == IQT_MEM.litValue).get
 
    require (mem_iq.issue_width == 1)
-   val iss_loadIssued = mem_iq.io.iss_valids(0) && mem_iq.io.iss_uops(0).is_load
+   val iss_loadIssued = mem_iq.io.iss_valids(0) && mem_iq.io.iss_uops(0).is_load && !mem_iq.io.iss_uops(0).fp_val
    val sxt_ldMiss =
       ((lsu.io.nack.valid && lsu.io.nack.isload) || dc_shim.io.core.load_miss) &&
       Pipe(true.B, iss_loadIssued, 4).bits

diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
@@ -77,7 +77,7 @@ class LoadStoreUnitIO(pl_width: Int)(implicit p: Parameters) extends BoomBundle(
 
    // Memory Stage
    val memreq_kill        = Bool(OUTPUT) // kill request sent out last cycle
-   val mem_ldSpecWakeup   = Valid(UInt(width=PREG_SZ.W))
+   val mem_ldSpecWakeup   = Valid(UInt(width=PREG_SZ.W)) // do NOT send out FP loads.
 
    // Forward Store Data to Register File
    // TODO turn into forward bundle
@@ -648,7 +648,7 @@ class LoadStoreUnit(pl_width: Int)(implicit p: Parameters, edge: freechips.rocke
       mem_ld_killed := Bool(true) && mem_fired_ld
    }
 
-   io.mem_ldSpecWakeup.valid := RegNext(will_fire_load_incoming, init=false.B)
+   io.mem_ldSpecWakeup.valid := RegNext(will_fire_load_incoming && !io.exe_resp.bits.uop.fp_val, init=false.B)
    io.mem_ldSpecWakeup.bits := mem_ld_uop.pdst
 
    // tell the ROB to clear the busy bit on the incoming store