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Merge branch 'spear/13xx' into next/soc2
* spear/13xx: pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res SPEAr: Update MAINTAINERS and Documentation SPEAr13xx: Add defconfig SPEAr13xx: Add compilation support SPEAr13xx: Add dts and dtsi files pinctrl: Add SPEAr13xx pinctrl drivers pinctrl: SPEAr: Create macro for declaring GPIO PINS SPEAr13xx: Add common clock framework support SPEAr13xx: Add source files SPEAr13xx: Add header files Depends on clock, pinctrl and dt branches to go first. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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| * SPEAr ARM Timer | ||
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| ** Timer node required properties: | ||
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| - compatible : Should be: | ||
| "st,spear-timer" | ||
| - reg: Address range of the timer registers | ||
| - interrupt-parent: Should be the phandle for the interrupt controller | ||
| that services interrupts for this device | ||
| - interrupt: Should contain the timer interrupt number | ||
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| Example: | ||
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| timer@f0000000 { | ||
| compatible = "st,spear-timer"; | ||
| reg = <0xf0000000 0x400>; | ||
| interrupts = <2>; | ||
| }; |
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Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
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| * Freescale IOMUX Controller (IOMUXC) for i.MX | ||
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| The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC | ||
| to share one PAD to several functional blocks. The sharing is done by | ||
| multiplexing the PAD input/output signals. For each PAD there are up to | ||
| 8 muxing options (called ALT modes). Since different modules require | ||
| different PAD settings (like pull up, keeper, etc) the IOMUXC controls | ||
| also the PAD settings parameters. | ||
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| Please refer to pinctrl-bindings.txt in this directory for details of the | ||
| common pinctrl bindings used by client devices, including the meaning of the | ||
| phrase "pin configuration node". | ||
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| Freescale IMX pin configuration node is a node of a group of pins which can be | ||
| used for a specific device or function. This node represents both mux and config | ||
| of the pins in that group. The 'mux' selects the function mode(also named mux | ||
| mode) this pin can work on and the 'config' configures various pad settings | ||
| such as pull-up, open drain, drive strength, etc. | ||
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| Required properties for iomux controller: | ||
| - compatible: "fsl,<soc>-iomuxc" | ||
| Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs. | ||
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| Required properties for pin configuration node: | ||
| - fsl,pins: two integers array, represents a group of pins mux and config | ||
| setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a | ||
| pin working on a specific function, CONFIG is the pad setting value like | ||
| pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid | ||
| pins and functions of each SoC. | ||
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| Bits used for CONFIG: | ||
| NO_PAD_CTL(1 << 31): indicate this pin does not need config. | ||
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| SION(1 << 30): Software Input On Field. | ||
| Force the selected mux mode input path no matter of MUX_MODE functionality. | ||
| By default the input path is determined by functionality of the selected | ||
| mux mode (regular). | ||
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| Other bits are used for PAD setting. | ||
| Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part | ||
| of bits definitions. | ||
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| NOTE: | ||
| Some requirements for using fsl,imx-pinctrl binding: | ||
| 1. We have pin function node defined under iomux controller node to represent | ||
| what pinmux functions this SoC supports. | ||
| 2. The pin configuration node intends to work on a specific function should | ||
| to be defined under that specific function node. | ||
| The function node's name should represent well about what function | ||
| this group of pins in this pin configuration node are working on. | ||
| 3. The driver can use the function node's name and pin configuration node's | ||
| name describe the pin function and group hierarchy. | ||
| For example, Linux IMX pinctrl driver takes the function node's name | ||
| as the function name and pin configuration node's name as group name to | ||
| create the map table. | ||
| 4. Each pin configuration node should have a phandle, devices can set pins | ||
| configurations by referring to the phandle of that pin configuration node. | ||
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| Examples: | ||
| usdhc@0219c000 { /* uSDHC4 */ | ||
| fsl,card-wired; | ||
| vmmc-supply = <®_3p3v>; | ||
| status = "okay"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&pinctrl_usdhc4_1>; | ||
| }; | ||
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| iomuxc@020e0000 { | ||
| compatible = "fsl,imx6q-iomuxc"; | ||
| reg = <0x020e0000 0x4000>; | ||
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| /* shared pinctrl settings */ | ||
| usdhc4 { | ||
| pinctrl_usdhc4_1: usdhc4grp-1 { | ||
| fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | ||
| 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | ||
| 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | ||
| 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | ||
| 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | ||
| 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | ||
| 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | ||
| 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | ||
| 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | ||
| 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | ||
| }; | ||
| }; | ||
| .... | ||
| }; | ||
| Refer to the IOMUXC controller chapter in imx6q datasheet, | ||
| 0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, | ||
| 80Ohm driver strength and Fast Slew Rate. | ||
| User should refer to each SoC spec to set the correct value. | ||
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| TODO: when dtc macro support is available, we can change above raw data | ||
| to dt macro which can get better readability in dts file. |
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