zephyr: add module.yml and fix riscv compile error (bytecodealliance#763

)
liangyongxiang · Sep 24, 2021 · 1ad76f4 · 1ad76f4
1 parent 7be0d38
commit 1ad76f4
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Showing 3 changed files with 7 additions and 2 deletions.
diff --git a/core/iwasm/aot/arch/aot_reloc_riscv.c b/core/iwasm/aot/arch/aot_reloc_riscv.c
@@ -77,7 +77,7 @@ rv_set_val(uint16 *addr, uint32 val)
     *addr = (val & 0xffff);
     *(addr + 1) = (val >> 16);
 
-    asm volatile("fence.i");
+    __asm__ volatile("fence.i");
 }
 
 /* Add a val to given address */

diff --git a/core/iwasm/aot/arch/aot_reloc_thumb.c b/core/iwasm/aot/arch/aot_reloc_thumb.c
@@ -153,7 +153,7 @@ get_target_symbol_map(uint32 *sym_num)
 void
 get_current_target(char *target_buf, uint32 target_buf_size)
 {
-    const char * s =  BUILD_TARGET;
+    const char *s = BUILD_TARGET;
     size_t s_size = sizeof(BUILD_TARGET);
     char *d = target_buf;
 

diff --git a/zephyr/module.yml b/zephyr/module.yml
@@ -0,0 +1,5 @@
+name: wasm-micro-runtime
+
+build:
+  cmake-ext: True
+  kconfig-ext: True