refactor(moe): migrate qwen3_moe onto the shared SwitchGLU

[inureyes]

Summary

qwen3_moe kept its own SwitchLinear, SwitchGLU and forward_fused_kernel, and qwen3_vl_moe (which also builds the Qwen3-Omni-MoE thinker) built that copy by hand. The copy never got the fused-kernel dff bound the shared type gained in #311 and #643, so MLXCEL_FUSED_MOE_MAX_DFF was silently ignored. Both families now hold switch_layers::SwitchGLU (SwitchGLU::from_weights, affine) and the copy is deleted rather than patched.

• Loader changes: bits are inferred from tensor shapes (the copy stored the configured value), a missing .biases plane fails through validate_quantization_biases instead of Weight not found, and unstacked experts.{idx} checkpoints now reach the shared stacking fallback. Every expert plane of the four local Qwen3-MoE checkpoints (safetensors headers) solves to 4-bit with biases shaped like the scales.
• Tests: the fix(models): bound quantization params in the family-local MoE expert loaders #958 guard tests drive each family's SparseMoeBlock::from_weights; new tests pin the Dff 8256 decline through both loaders (positive control at Dff 64 only when custom_kernels_available(), refactor(core): route custom kernels by GPU backend kind instead of treating every non-Metal GPU as CUDA #1803) and the mxfp4 decline.
• Docs: switch_layers.rs, docs/environment-variables.md and the fused-MoE design note now say which families read the bound, fix the family counts, and qualify the qwen3-30b-a3b greedy parity claim.

Verification (GB10 sm_121, release --features cuda, base b8d10fb1)

• Greedy ids (64 tokens, -t 0, as ids): identical base vs branch on qwen3-30b-a3b-4bit, qwen3-vl-30b-a3b-4bit and the qwen3-omni-30b-a3b-instruct-4bit thinker, default fused and MLXCEL_FUSED_MOE=0. Fused and gather diverge from each other at token 39 (qwen3-30b) and 26 (omni) on both binaries, so the fused match also rules out a silent fallback.
• Trace (MLXCEL_PROFILE_BLOCKS=1 MLXCEL_PROFILE_QWEN3_MOE_DETAIL=1, -n 4): 144 path=fused tokens=1, 0 path=gather_qmm tokens=1 on both binaries.
• The bound now applies: with MLXCEL_FUSED_MOE_MAX_DFF=512 the base trace stays 144 fused and the branch is 144 path=gather_qmm tokens=1; omni base ids equal its fused ids and branch ids equal its MLXCEL_FUSED_MOE=0 ids; VL 64-token runs stay at 2.31 to 2.35 s on base (kernel launched) and drop to 1.28 to 1.33 s on the branch.
• mlxcel-server, temperature 0: identical content and reasoning base vs branch on qwen3-30b and VL; the VL completion is coherent and opens with the CLI's tokens.
• Decode tok/s, qwen3-30b (mlxcel-bench-decode -n 128 --ignore-eos --warmup-tokens 20), 15 interleaved runs per arm: base 66.21 to 87.76 (median 78.00), branch 61.27 to 86.28 (median 73.63). Decode here is bimodal; high-mode means 81.06 vs 79.65, Mann-Whitney p = 0.21.
• 38 of 38 tests under models::qwen3_moe, models::qwen3_vl_moe, models::switch_layers pass, one process each; both new decline tests fail against a mutant with the bound disabled. Scoped clippy (-p mlxcel --lib --tests --features cuda -D warnings) and fmt are clean. Ids, trace, cap and server checks were repeated with binaries rebuilt at the final commit.
• Not run: metal,accelerate gate (Linux host), workspace-wide verify-test-cuda. The OpenXLA feature compile CI failure also fails on main at b8d10fb1 (unused imports in models/mod.rs and server modules) and is unrelated.

Follow-up candidates

qwen3_next.rs (same kernel copy and missing guards), gemma4.rs (GeGLU, no bound), NemotronH's opt-in MLXCEL_FUSED_MOE_RELU2 path, ten families with a local SwitchGLU and no fused path, a cached bound instead of a per-call env read, and pre-existing shared-loader gaps found in review (no cross-plane or router-vs-expert-count check; the unstacked fallback does not compare shapes before stack).

Closes #1884