FPU

A floating point multicycle ALU for Computer Architecture 2014. Ideally, implements ADD, SUBTRACT, MULT

Full documentation can be found at the Olin Computer Architecture 2014 Course website:

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
work		work
.gitignore		.gitignore
README.md		README.md
SLT.v		SLT.v
adder.v		adder.v
complete_add.v		complete_add.v
exp.v		exp.v
fpu.v		fpu.v
modelsim.ini		modelsim.ini
multiplier.v		multiplier.v
support_modules.v		support_modules.v
test_SLT.do		test_SLT.do
test_complete_add.do		test_complete_add.do
test_csa.do		test_csa.do
test_fpu.do		test_fpu.do
test_mult.do		test_mult.do
test_negate.do		test_negate.do
vsim.wlf		vsim.wlf
wlftst2nvy		wlftst2nvy

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