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drm/amdgpu: Skip access PF-only registers on gfx10/gfxhub2_1 under SRIOV
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[Why]
RLCG interface returns "out-of-range" error under SRIOV VF when accessing
PF-only registers.

[How]
Skip access PF-only registers on gfx10/gfxhub2_1 under SRIOV.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ZhenGuo Yin authored and alexdeucher committed Mar 20, 2024
1 parent f679fd6 commit 56b30ac
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Showing 2 changed files with 9 additions and 2 deletions.
8 changes: 6 additions & 2 deletions drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
Original file line number Diff line number Diff line change
Expand Up @@ -3657,6 +3657,9 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)

static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
{
if (amdgpu_sriov_vf(adev))
return;

switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(10, 1, 10):
soc15_program_register_sequence(adev,
Expand Down Expand Up @@ -4982,7 +4985,8 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
u32 tmp;
int i;

WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
if (!amdgpu_sriov_vf(adev))
WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);

gfx_v10_0_setup_rb(adev);
gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
Expand Down Expand Up @@ -7163,7 +7167,7 @@ static int gfx_v10_0_hw_init(void *handle)
if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
gfx_v10_3_program_pbb_mode(adev);

if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
gfx_v10_3_set_power_brake_sequence(adev);

return r;
Expand Down
3 changes: 3 additions & 0 deletions drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,9 @@ static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
{
uint64_t value;

if (amdgpu_sriov_vf(adev))
return;

/* Program the AGP BAR */
WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
Expand Down

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