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Commits on Apr 3, 2024

• Assembler: implement GAS modifiers

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Commits on Dec 9, 2023

• Machine: propagate ISA flags into misa CSR register

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Commits on Dec 2, 2023

• Machine: restrict more CSR registers fields to read only and correct CYCLE CSR updates

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• Machine: extend CSR support to pass rv32mi-p-mcsr and rv64mi-p-mcsr official test

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Commits on Nov 26, 2023

• Merge branch 'irq-support' with basic interrupt support usable for serial port

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Commits on Nov 25, 2023

• Machine: redefine exception codes to match RISC-V s/mcause register.

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• Machine: CSR: basic exceptions support functional for external interrupts

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Commits on Nov 24, 2023

• CLI: Add test for issue cvut#88

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Commits on Nov 28, 2022

• Machine: CSR: update cli test expected output to include mie.

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Commits on Oct 19, 2022

• Machine: CSR: update cli test expected output

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Commits on Sep 11, 2022

• qtrvsim_tester: CLANG and GCC options to match real 32 and 64-bit targets

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• qtrvsim_tester: modify CHECK_XLEN to report fail in the case of unexpected XLEN

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Commits on Sep 7, 2022

• qtrvsim_tester: update README.md to reflect that it has been added as a subtree

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• qtrvsim_tester: found out that Ubuntu18 has too old Python stdlib

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• qtrvsim_tester: make work with clang

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• qtrvsim_tester: selftests add

  

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• qtrvsim_tester: selftest organization

  

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• qtrvsim_tester: update README.md

  

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• qtrvsim_tester: minor repairs

  

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• qtrvsim_tester: code split into multiple files, basic selftest implemented

  

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• qtrvsim_tester: renamed entrypoint

  

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• qtrvsim_tester: code cleaning and quality of life help update

  

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• qtrvsim_tester: better help print when error occurs

  

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• qtrvsim_tester: arguments added, support for multiply, atomic and CSR

  

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• qtrvsim_tester: sync

  

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• qtrvsim_tester: color in term

  

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• qtrvsim_tester: file count change

  

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• qtrvsim_tester: filler files

  

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• qtrvsim_tester: readme edit

  

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• qtrvsim_tester: added submodule and made outup more pretty

  

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• qtrvsim_tester: initial commit

  

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Commits on Mar 26, 2022

• Machine: remap MIPS Cop0 matching registers to RISC-V CSRs counterparts.

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Commits on Mar 6, 2022

• CI: update simple cli test to reflect change of sp register to x2.

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Commits on Feb 14, 2022

• CI: update simple cli test to match new start 0x200 address.

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Commits on Dec 17, 2021

• CI: add first cli test

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