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Improve timer and fix some instruction mcycles
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@linoscope
linoscope committed Oct 21, 2021
1 parent 31407e7 commit 9c54b4c
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Showing 7 changed files with 42 additions and 29 deletions.
10 changes: 5 additions & 5 deletions lib/cpu/fetch_and_decode.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -120,23 +120,23 @@ module Make (Mmu : Word_addressable_intf.S) = struct
| 0x5B -> l1, (1, 1), LD8 (R E, R E)
| 0x5C -> l1, (1, 1), LD8 (R E, R H)
| 0x5D -> l1, (1, 1), LD8 (R E, R L)
| 0x5E -> l1, (1, 1), LD8 (R E, RR_indirect HL)
| 0x5E -> l1, (2, 2), LD8 (R E, RR_indirect HL)
| 0x5F -> l1, (1, 1), LD8 (R E, R A)
| 0x60 -> l1, (1, 1), LD8 (R H, R B)
| 0x61 -> l1, (1, 1), LD8 (R H, R C)
| 0x62 -> l1, (1, 1), LD8 (R H, R D)
| 0x63 -> l1, (1, 1), LD8 (R H, R E)
| 0x64 -> l1, (1, 1), LD8 (R H, R H)
| 0x65 -> l1, (1, 1), LD8 (R H, R L)
| 0x66 -> l1, (1, 1), LD8 (R H, RR_indirect HL)
| 0x66 -> l1, (2, 2), LD8 (R H, RR_indirect HL)
| 0x67 -> l1, (1, 1), LD8 (R H, R A)
| 0x68 -> l1, (1, 1), LD8 (R L, R B)
| 0x69 -> l1, (1, 1), LD8 (R L, R C)
| 0x6A -> l1, (1, 1), LD8 (R L, R D)
| 0x6B -> l1, (1, 1), LD8 (R L, R E)
| 0x6C -> l1, (1, 1), LD8 (R L, R H)
| 0x6D -> l1, (1, 1), LD8 (R L, R L)
| 0x6E -> l1, (1, 1), LD8 (R L, RR_indirect HL)
| 0x6E -> l1, (2, 2), LD8 (R L, RR_indirect HL)
| 0x6F -> l1, (1, 1), LD8 (R L, R A)
| 0x70 -> l1, (2, 2), LD8 (RR_indirect HL, R B)
| 0x71 -> l1, (2, 2), LD8 (RR_indirect HL, R C)
Expand Down Expand Up @@ -223,7 +223,7 @@ module Make (Mmu : Word_addressable_intf.S) = struct
| 0xC2 -> l3, (3, 4), JP (NZ, Immediate16 (next_word ()))
| 0xC3 -> l3, (4, 4), JP (None, Immediate16 (next_word ()))
| 0xC4 -> l3, (3, 6), CALL (NZ, next_word ())
| 0xC5 -> l1, (1, 4), PUSH BC
| 0xC5 -> l1, (4, 4), PUSH BC
| 0xC6 -> l2, (2, 2), ADD8 (R A, (Immediate8 (next_byte ())))
| 0xC7 -> l1, (4, 4), RST RST_offset.x00
| 0xC8 -> l1, (2, 5), RET Z
Expand All @@ -238,7 +238,7 @@ module Make (Mmu : Word_addressable_intf.S) = struct
| 0xD2 -> l3, (3, 4), JP (NC, Immediate16 (next_word ()))
| 0xD3 -> l1, (1, 1), NOP
| 0xD4 -> l3, (3, 6), CALL (NC, next_word ())
| 0xD5 -> l1, (1, 4), PUSH DE
| 0xD5 -> l1, (4, 4), PUSH DE
| 0xD6 -> l2, (2, 2), SUB (R A, Immediate8 (next_byte ()))
| 0xD7 -> l1, (4, 4), RST RST_offset.x10
| 0xD8 -> l1, (2, 5), RET C
Expand Down
8 changes: 4 additions & 4 deletions lib/joypad/joypad.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -70,8 +70,8 @@ let read_byte t _ =
match t.mode with
| Direction ->
Bit_util.byte_of_bitflags
false
false
true
true
false
true
(t.down |> Key_state.to_bool)
Expand All @@ -80,8 +80,8 @@ let read_byte t _ =
(t.right |> Key_state.to_bool)
| Action ->
Bit_util.byte_of_bitflags
false
false
true
true
true
false
(t.start |> Key_state.to_bool)
Expand Down
23 changes: 13 additions & 10 deletions lib/timer/timer_counter.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,10 @@ end = struct

(* cpu mclock: 1048576 Hz
* timer mclock:
* - 00: 4096 Hz => cpu mclock / timer mclock = 256
* - 00: 4096 Hz => cpu mclock / timer mclock = 256
* - 01: 262144 Hz => cpu mclock / timer mclock = 4
* - 10: 65536 Hz => cpu mclock / timer mclock = 16
* - 11: 16384 Hz => cpu mclock / timer mclock = 64
* - 10: 65536 Hz => cpu mclock / timer mclock = 16
* - 11: 16384 Hz => cpu mclock / timer mclock = 64
* *)
let of_byte u8 =
let open Uint8 in
Expand Down Expand Up @@ -62,22 +62,23 @@ let run t ~mcycles =
if t.is_running then begin
t.uncounted_mcycles <- t.uncounted_mcycles + mcycles;
let mcycle_per_count = Speed.mcycle_per_count t.speed in
while t.uncounted_mcycles >= mcycle_per_count do
t.uncounted_mcycles <- t.uncounted_mcycles - mcycle_per_count;
t.count <- t.count + 1;
if t.count >= 0xFF then begin
if t.uncounted_mcycles >= mcycle_per_count then begin
t.count <- t.count + (t.uncounted_mcycles / mcycle_per_count);
t.uncounted_mcycles <- t.uncounted_mcycles mod mcycle_per_count;
if t.count > 0xFF then begin
Interrupt_controller.request t.ic Timer;
t.count <- t.modulo
end
done
end
end

let accepts t addr =
Uint16.(addr = t.tima_addr || addr = t.tma_addr || addr = t.tac_addr)

let read_byte t addr =
match addr with
| _ when Uint16.(addr = t.tima_addr) -> t.count |> Uint8.of_int
| _ when Uint16.(addr = t.tima_addr) ->
t.count |> Uint8.of_int
| _ when Uint16.(addr = t.tma_addr) -> t.modulo |> Uint8.of_int
| _ when Uint16.(addr = t.tac_addr) ->
let open Uint8 in
Expand All @@ -92,5 +93,7 @@ let write_byte t ~addr ~data =
| _ when Uint16.(addr = t.tma_addr) -> t.modulo <- Uint8.to_int data
| _ when Uint16.(addr = t.tac_addr) ->
t.speed <- Speed.of_byte data;
t.is_running <- Uint8.(data land of_int 0b100 <> zero)
t.is_running <- Uint8.(data land of_int 0b100 <> zero);
if not t.is_running then
t.uncounted_mcycles <- 0
| _ -> raise @@ Invalid_argument "Address out of bounds"
6 changes: 2 additions & 4 deletions test/rom_tests/test_blargg_test_roms.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,5 @@ let%expect_test "instr_timing.gb" =
[%expect {|
instr_timing


Timer doesn't work properly

Failed #2 |}]
CB 46:4-3 CB 4E:4-3 CB 56:4-3 CB 5E:4-3 CB 66:4-3 CB 6E:4-3 CB 76:4-3 CB 7E:4-3
Failed |}]
10 changes: 5 additions & 5 deletions test/unit_tests/test_fetch_and_decode.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -491,7 +491,7 @@ let%expect_test "test all instructions" =
{
inst = LD E, (HL);
inst_len = 1;
mcycles = (1, 1)
mcycles = (2, 2)
}
{
inst = LD E, A;
Expand Down Expand Up @@ -531,7 +531,7 @@ let%expect_test "test all instructions" =
{
inst = LD H, (HL);
inst_len = 1;
mcycles = (1, 1)
mcycles = (2, 2)
}
{
inst = LD H, A;
Expand Down Expand Up @@ -571,7 +571,7 @@ let%expect_test "test all instructions" =
{
inst = LD L, (HL);
inst_len = 1;
mcycles = (1, 1)
mcycles = (2, 2)
}
{
inst = LD L, A;
Expand Down Expand Up @@ -1006,7 +1006,7 @@ let%expect_test "test all instructions" =
{
inst = PUSH BC;
inst_len = 1;
mcycles = (1, 4)
mcycles = (4, 4)
}
{
inst = ADD A, $AB;
Expand Down Expand Up @@ -2361,7 +2361,7 @@ let%expect_test "test all instructions" =
{
inst = PUSH DE;
inst_len = 1;
mcycles = (1, 4)
mcycles = (4, 4)
}
{
inst = SUB A, $AB;
Expand Down
12 changes: 12 additions & 0 deletions test/unit_tests/test_joypad.ml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
open Camlboy_lib
open Uints

let%expect_test "test initial value" =
let addr = (Uint16.of_int 0xFF00) in
let t = Joypad.create ~addr in

Joypad.read_byte t addr
|> Uint8.show
|> print_endline;

[%expect {| $DF |}]
2 changes: 1 addition & 1 deletion test/unit_tests/test_oam_table.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -23,4 +23,4 @@ let%expect_test "test" =

[%expect {|
{ Oam_table.y_pos = 104; x_pos = 69; tile_index = $90;
priority = `Sprite_bottom; y_flip = false; x_flip = true; pallete = `OBP1 } |}]
priority = `Sprite_top; y_flip = false; x_flip = true; pallete = `OBP1 } |}]

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