Added ShiftRight and Erasable Bank Register with unit tests

Cleaned up and refactore some code
jnosek · Jul 6, 2017 · 5649543 · 5649543
1 parent 149b478
commit 5649543
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Showing 11 changed files with 202 additions and 22 deletions.
diff --git a/AGC/AGC.csproj b/AGC/AGC.csproj
@@ -40,6 +40,7 @@
     <Compile Include="Core\DoublePrecision.cs" />
     <Compile Include="Architecture\QuarterCodeInstructionList.cs" />
     <Compile Include="Core\FixedMemory.cs" />
+    <Compile Include="Registers\ErasableBankRegister.cs" />
     <Compile Include="Registers\FullRegister.cs" />
     <Compile Include="Core\MemoryBankOffset.cs" />
     <Compile Include="Core\OnesCompliment.cs" />
@@ -73,6 +74,7 @@
     <Compile Include="Properties\AssemblyInfo.cs" />
     <Compile Include="Registers\Accumulator.cs" />
     <Compile Include="Registers\ProgramCounter.cs" />
+    <Compile Include="Registers\ShiftRightRegister.cs" />
   </ItemGroup>
   <Import Project="$(MSBuildExtensionsPath32)\Microsoft\Portable\$(TargetFrameworkVersion)\Microsoft.Portable.CSharp.targets" />
   <!-- To modify your build process, add your task inside one of the targets below and uncomment it. 

diff --git a/AGC/Core/DoublePrecision.cs b/AGC/Core/DoublePrecision.cs
@@ -5,7 +5,9 @@
 
 namespace Apollo.Virtual.AGC.Core
 {
-    // https://github.com/rburkey2005/virtualagc/blob/master/yaAGC/agc_engine.c
+    /// <summary>
+    /// https://github.com/rburkey2005/virtualagc/blob/master/yaAGC/agc_engine.c 
+    /// </summary>
     public class DoublePrecision
     {
         public SinglePrecision MostSignificantWord { get; protected set; }

diff --git a/AGC/ExtraCodeInstructionSet.cs b/AGC/ExtraCodeInstructionSet.cs
@@ -18,13 +18,5 @@ public ExtraCodeInstructionSet()
             Add(new ExtraQuarterCode3());
             Add(new BranchZeroOrMinusToFixed());
         }
-
-        public new IInstruction this[ushort code]
-        {
-            get
-            {
-                return base[code];
-            }
-        }
     }
 }
diff --git a/AGC/InstructionSet.cs b/AGC/InstructionSet.cs
@@ -23,13 +23,5 @@ public InstructionSet()
             Add(new CountCompareAndSkip());
             Add(new ClearAndSubtract());
         }
-
-        public new IInstruction this[ushort code]
-        {
-            get
-            {
-                return base[code];
-            }
-        }
     }
 }
diff --git a/AGC/Processor.cs b/AGC/Processor.cs
@@ -231,7 +231,7 @@ public Processor(MemoryMap memory)
             A = memory.AddRegister<Accumulator>();
             L = memory.AddRegister<FullRegister>(0x01);
             Q = memory.AddRegister<FullRegister>(0x02);
-            EB = memory.GetWord(0x3);
+            EB = memory.AddRegister<ErasableBankRegister>();
             FB = memory.GetWord(0x4);
             Z = memory.AddRegister<ProgramCounter>();
             BB = memory.GetWord(0x6);
@@ -249,7 +249,7 @@ public Processor(MemoryMap memory)
 
             // editing registers
             CYR = memory.AddRegister<CycleRightRegister>();
-            SR = memory.GetWord(0x11);
+            SR = memory.AddRegister<ShiftRightRegister>();
             CYL = memory.GetWord(0x12);
             EDOP = memory.GetWord(0x13);
 

diff --git a/AGC/Registers/ErasableBankRegister.cs b/AGC/Registers/ErasableBankRegister.cs
@@ -0,0 +1,29 @@
+using Apollo.Virtual.AGC.Core;
+using System;
+using System.Collections.Generic;
+using System.Linq;
+using System.Text;
+
+namespace Apollo.Virtual.AGC.Registers
+{
+    class ErasableBankRegister : MemoryAddress, IWord
+    {
+        public ErasableBankRegister(MemoryBank bank) : 
+            base(0x03, bank)
+        {
+        }
+
+        public ushort Read()
+        {
+            var v = new OnesCompliment(Get());
+            v.SignExtend();
+            return v;
+        }
+
+        public void Write(ushort value)
+        {
+            // can only set the 3 bits for the erasable memory bank selection
+            Set(value & 0x0700);
+        }
+    }
+}
diff --git a/AGC/Registers/ShiftRightRegister.cs b/AGC/Registers/ShiftRightRegister.cs
@@ -0,0 +1,38 @@
+using Apollo.Virtual.AGC.Core;
+using System;
+using System.Collections.Generic;
+using System.Linq;
+using System.Text;
+
+namespace Apollo.Virtual.AGC.Registers
+{
+    class ShiftRightRegister : MemoryAddress, IWord
+    {
+        public ShiftRightRegister(MemoryBank bank) 
+            : base(0x11, bank)
+        {
+        }
+
+        public ushort Read()
+        {
+            var v = new OnesCompliment(Get());
+            v.SignExtend();
+            return v;
+        }
+
+        public void Write(ushort value)
+        {
+            // first overflow correct the value
+            var v = new OnesCompliment(value);
+            v.OverflowCorrect();
+
+            value = v;
+
+            // preserve MSB and OR with shifted bits
+            var bits = (value & 0x4000) | (value >> 1);
+
+            // write the shifted value into memory
+            Set(bits);
+        }
+    }
+}
diff --git a/Tests/AGC.Tests/AGC.Tests.csproj b/Tests/AGC.Tests/AGC.Tests.csproj
@@ -62,6 +62,8 @@
     <Compile Include="Instructions\DoubleAddToStorage.cs" />
     <Compile Include="Properties\AssemblyInfo.cs" />
     <Compile Include="Registers\CycleRightRegister.cs" />
+    <Compile Include="Registers\ErasableBankRegister.cs" />
+    <Compile Include="Registers\ShiftRightRegister.cs" />
   </ItemGroup>
   <ItemGroup>
     <ProjectReference Include="..\..\AGC\AGC.csproj">

diff --git a/Tests/AGC.Tests/Registers/CycleRightRegister.cs b/Tests/AGC.Tests/Registers/CycleRightRegister.cs
@@ -11,7 +11,7 @@ namespace AGC.Tests.Registers
     public class CycleRightRegister : BaseTest
     {
         [TestMethod]
-        public void CycleRightOneWrapAround()
+        public void CycleRight_OneWrapAround()
         {
             // arrange
             Memory[0x200] = 51;
@@ -27,11 +27,11 @@ public void CycleRightOneWrapAround()
             CPU.Execute();
 
             // assert
-            Assert.AreEqual(0XC019, Memory[0x10]);
+            Assert.AreEqual(0xC019, Memory[0x10]);
         }
 
         [TestMethod]
-        public void CycleRightZeroWrapAround()
+        public void CycleRight_ZeroWrapAround()
         {
             // arrange
             Memory[0x200] = 50;

diff --git a/Tests/AGC.Tests/Registers/ErasableBankRegister.cs b/Tests/AGC.Tests/Registers/ErasableBankRegister.cs
@@ -0,0 +1,48 @@
+using Microsoft.VisualStudio.TestTools.UnitTesting;
+
+namespace AGC.Tests.Registers
+{
+    [TestClass]
+    public class ErasableBankRegister : BaseTest
+    {
+        [TestMethod]
+        public void ErasableBank_SetWithinMask()
+        {
+            // arrange
+            Memory[0x200] = 0x0200;
+
+            // insert instructions
+            Memory.LoadFixedRom(new ushort[] {
+                0x06000 | 0x200, // add to the accumulator
+                0x05800 | 0x03  // transfer to storage, the EB register
+            });
+
+            // act - run the instructions
+            CPU.Execute();
+            CPU.Execute();
+
+            // assert
+            Assert.AreEqual(0x0200, Memory[0x3]);
+        }
+
+        [TestMethod]
+        public void ErasableBank_SetOutsideMask()
+        {
+            // arrange
+            Memory[0x200] = 0x0002;
+
+            // insert instructions
+            Memory.LoadFixedRom(new ushort[] {
+                0x06000 | 0x200, // add to the accumulator
+                0x05800 | 0x03  // transfer to storage, the EB register
+            });
+
+            // act - run the instructions
+            CPU.Execute();
+            CPU.Execute();
+
+            // assert
+            Assert.AreEqual(0x0, Memory[0x3]);
+        }
+    }
+}
diff --git a/Tests/AGC.Tests/Registers/ShiftRightRegister.cs b/Tests/AGC.Tests/Registers/ShiftRightRegister.cs
@@ -0,0 +1,75 @@
+using Apollo.Virtual.AGC.Core;
+using Microsoft.VisualStudio.TestTools.UnitTesting;
+using System;
+using System.Collections.Generic;
+using System.Linq;
+using System.Text;
+using System.Threading.Tasks;
+
+namespace AGC.Tests.Registers
+{
+    [TestClass]
+    public class ShiftRightRegister : BaseTest
+    {
+        [TestMethod]
+        public void ShiftRight_Default()
+        {
+            // arrange
+            Memory[0x200] = 0x202;
+
+            // insert instructions
+            Memory.LoadFixedRom(new ushort[] {
+                0x06000 | 0x200, // add to the accumulator
+                0x05800 | 0x011  // transfer to storage, the SR register
+            });
+
+            // act - run the instructions
+            CPU.Execute();
+            CPU.Execute();
+
+            // assert
+            Assert.AreEqual(0x0101, Memory[0x11]);
+        }
+
+        [TestMethod]
+        public void ShiftRight_ClearLSB()
+        {
+            // arrange
+            Memory[0x200] = 0x201;
+
+            // insert instructions
+            Memory.LoadFixedRom(new ushort[] {
+                0x06000 | 0x200, // add to the accumulator
+                0x05800 | 0x011  // transfer to storage, the SR register
+            });
+
+            // act - run the instructions
+            CPU.Execute();
+            CPU.Execute();
+
+            // assert
+            Assert.AreEqual(0x0100, Memory[0x11]);
+        }
+
+        [TestMethod]
+        public void ShiftRight_DuplicateMSB()
+        {
+            // arrange
+            Memory[0x200] = 0xC000; // sign extended 0x4000 value
+
+            // insert instructions
+            Memory.LoadFixedRom(new ushort[] {
+                0x06000 | 0x200, // add to the accumulator
+                0x05800 | 0x011  // transfer to storage, the SR register
+            });
+
+            // act - run the instructions
+            CPU.Execute();
+            CPU.Execute();
+
+            // assert
+            // sign extended 0x6000 value
+            Assert.AreEqual(0xE000, Memory[0x11]);
+        }
+    }
+}