Support 64-bit values for CP0 Context. Correct write masking for Cont…

…ext and XContext.
jlippitt · May 14, 2024 · a7aed06 · a7aed06
1 parent 14185d2
commit a7aed06
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/system/src/cpu/cp0.rs b/system/src/cpu/cp0.rs
@@ -66,7 +66,7 @@ impl Cp0 {
             1 => self.regs.random as i32 as i64,
             2 => u32::from(self.regs.entry_lo0) as i32 as i64,
             3 => u32::from(self.regs.entry_lo1) as i32 as i64,
-            4 => u32::from(self.regs.context) as i32 as i64,
+            4 => u64::from(self.regs.context) as i64,
             5 => u32::from(self.regs.page_mask) as i32 as i64,
             6 => self.regs.wired as i32 as i64,
             8 => self.regs.bad_vaddr as i32 as i64,
@@ -101,7 +101,7 @@ impl Cp0 {
                 trace!("  EntryLo1: {:?}", self.regs.entry_lo1);
             }
             4 => {
-                self.regs.context = (value as u32).into();
+                self.regs.context = (value as u64 & 0xffff_ffff_ff80_0000).into();
                 trace!("  Context: {:?}", self.regs.context);
             }
             5 => {
@@ -185,7 +185,7 @@ impl Cp0 {
                 trace!("  WatchHi: {:?}", self.regs.watch_hi);
             }
             20 => {
-                self.regs.x_context = (value as u64).into();
+                self.regs.x_context = (value as u64 & 0xffff_fffe_0000_0000).into();
                 trace!("  XContext: {:?}", self.regs.x_context);
             }
             // TOOD: This register has special behaviour when read back

diff --git a/system/src/cpu/cp0/regs.rs b/system/src/cpu/cp0/regs.rs
@@ -85,14 +85,15 @@ pub struct EntryLo {
     __: u32,
 }
 
-#[bitfield(u32)]
+#[bitfield(u64)]
 pub struct Context {
     #[bits(4)]
     __: u32,
     #[bits(19)]
     pub bad_vpn2: u32,
     #[bits(9)]
     pub pte_base: u32,
+    pub __: u32,
 }
 
 #[bitfield(u32)]