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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351377 91177308-0d34-0410-b5e6-96231b3b80d8
…ctWithAllOnesOrZeros If we're going to generate a new inverted setcc, we should make sure we will be able to remove the old setcc. Differential Revision: https://reviews.llvm.org/D56765 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351378 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: For these loads that write to the HI part of a register, we should chain them to the op that writes to the LO part of the register to maintain the appropriate order. Reviewers: rampitec, arsenm Differential Revision: https://reviews.llvm.org/D56454 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351379 91177308-0d34-0410-b5e6-96231b3b80d8
…blendv just before isel table lookup. Remove vselect isel patterns. This cleans up the duplication we have with both intrinsic isel patterns and vselect isel patterns. This should also allow the intrinsics to get SimplifyDemandedBits support for the condition. I've switched the canonical pattern in isel to use the X86ISD::BLENDV node instead of VSELECT. Since it always seemed weird to move from BLENDV with its relaxed rules on condition bits to VSELECT which has strict rules about all bits of the condition element being the same. Its more correct to go from VSELECT to BLENDV. Differential Revision: https://reviews.llvm.org/D56771 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351380 91177308-0d34-0410-b5e6-96231b3b80d8
Previously we used ISD::SHL and ISD::SRL to represent these in SelectionDAG. ISD::SHL/SRL interpret an out of range shift amount as undefined behavior and will constant fold to undef. While the intrinsics are defined to return 0 for out of range shift amounts. A previous patch added a special node for VPSRAV to produce all sign bits. This was previously believed safe because undefs frequently get turned into 0 either from the constant pool or a desire to not have a false register dependency. But undef is treated specially in some optimizations. For example, its ignored in detection of vector splats. So if the ISD::SHL/SRL can be constant folded and all of the elements with in bounds shift amounts are the same, we might fold it to single element broadcast from the constant pool. This would not put 0s in the elements with out of bounds shift amounts. We do have an existing InstCombine optimization to use shl/lshr when the shift amounts are all constant and in bounds. That should prevent some loss of constant folding from this change. Patch by zhutianyang and Craig Topper Differential Revision: https://reviews.llvm.org/D56695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351381 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351384 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351386 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: This change factors out compiler checking / warning, and documents LLVM_FORCE_USE_OLD_TOOLCHAIN. It doesn't introduce any functional changes nor policy changes, these will come late. Subscribers: mgorny, jkorous, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D56799 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351387 91177308-0d34-0410-b5e6-96231b3b80d8
…t. NFC. Differential Revision: https://reviews.llvm.org/D56809 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351388 91177308-0d34-0410-b5e6-96231b3b80d8
…n for custom handling in clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351389 91177308-0d34-0410-b5e6-96231b3b80d8
Currently we have pgo options defined in PassManagerBuilder.cpp only for instrument pgo, but not for sample pgo. We also have pgo options defined in NewPMDriver.cpp in opt only for new pass manager and for all kinds of pgo. They have some inconsistency. To make the options more consistent and make tests writing easier, the patch let old pass manager to share the same pgo options with new pass manager in opt, and removes the options in PassManagerBuilder.cpp. Differential Revision: https://reviews.llvm.org/D56749 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351392 91177308-0d34-0410-b5e6-96231b3b80d8
Currently we do not always collapse subsequent .loc 0 0 directives. The
reason is that we were checking for a PrevInstLoc which is not set when
we emit a line-0 record. We should only check the LastAsmLine, which
seems to be created exactly for this purpose.
// When we emit a line-0 record, we don't update PrevInstLoc; so look at
// the last line number actually emitted, to see if it was line 0.
unsigned LastAsmLine =
Asm->OutStreamer->getContext().getCurrentDwarfLoc().getLine();
Differential revision: https://reviews.llvm.org/D56767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351395 91177308-0d34-0410-b5e6-96231b3b80d8
PGOInstrGen should be initialized to "" instead of false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351397 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: Everything before the word "version" is the tool, and everything after the word "version" is the version. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D56742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351399 91177308-0d34-0410-b5e6-96231b3b80d8
Also, fix a few existing links so they don't require registration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351403 91177308-0d34-0410-b5e6-96231b3b80d8
The Windows ARM64 runtime passes the establisher frame to funclets as the first argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351404 91177308-0d34-0410-b5e6-96231b3b80d8
Essentially, do not treat `call` and `musttail call` as the same thing. As a drive-by, fold CallInst and InvokeInst handling together using the CallSite helper. Differential Revision: https://reviews.llvm.org/D56815 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351405 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351406 91177308-0d34-0410-b5e6-96231b3b80d8
…t use scalar integers for mask. We will custom emit these builtins in clang using the new intrinsics that take a vXi1 mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351407 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts commit eccdbba3a02a33e13b5262e92200a33e2ead873d. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351410 91177308-0d34-0410-b5e6-96231b3b80d8
The function merging pass miscompiles identical vararg functions. The forwarding thunk it emits doesn't forward the full variable-length list of arguments. Disable merging for vararg functions for now. I've filed llvm.org/PR40345 to track the issue. rdar://47326238 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351411 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351413 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351416 91177308-0d34-0410-b5e6-96231b3b80d8
This refactors the getRelocationValueString method. It is a bit overcomplicated and it is possible to reduce it without losing the functionality it seems. Differential revision: https://reviews.llvm.org/D56778 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351417 91177308-0d34-0410-b5e6-96231b3b80d8
Forgot to address this one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351418 91177308-0d34-0410-b5e6-96231b3b80d8
There are cases where we have multiple epilogues that have the exact same unwind code sequence. In that case, the epilogues can share the same unwind codes in the .xdata section. This should get us past the assert "SEH unwind data splitting not yet implemented" in many cases. We still need to add support for generating multiple .pdata/.xdata sections for those functions that need to be split into fragments. Differential Revision: https://reviews.llvm.org/D56813 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351421 91177308-0d34-0410-b5e6-96231b3b80d8
In order to support codegen RV64A, this patch: * Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg that use the i64 type. These are ultimately lowered to masked operations using lr.w/sc.w, but we need to use these alternate intrinsics for RV64 because i32 is not legal * Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and PseudoCmpXchg64 * Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as needed for RV64 and to select the i64 intrinsic IDs when necessary * Adds appropriate patterns to RISCVInstrInfoA.td * Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support This ends up being a fairly mechanical change, as the logic for RV32A is effectively reused. Differential Revision: https://reviews.llvm.org/D53233 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351422 91177308-0d34-0410-b5e6-96231b3b80d8
Allow varargs functions to be called, both in arm and thumb mode. This boils down to choosing the correct calling convention, which we can easily test by making sure arm_aapcscc is used instead of arm_aapcs_vfpcc when the callee is variadic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351424 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351425 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351426 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid the infinite loop caused by the target DAG combine converting ANYEXT to SIGNEXT and the target-independent DAG combine logic converting back to ANYEXT. Do this by not adding the new node to the worklist. Committing directly as this definitely doesn't make the problem any worse, and I intend to follow-up with a patch that avoids this custom combiner logic altogether and just lowers the i32 operations to a target-specific SelectionDAG node. This should be easier to reason about and improve codegen quality in some cases (though may miss out on some later DAG combines). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351806 91177308-0d34-0410-b5e6-96231b3b80d8
When we are inserting 1 "inline" element, and zeroing 2 of the other elements then we can safely commute the insertps source inputs to improve memory folding. Differential Revision: https://reviews.llvm.org/D56843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351807 91177308-0d34-0410-b5e6-96231b3b80d8
First step towards PR40376, this patch adds support for getCmpSelInstrCost to use the (optional) Instruction CmpInst predicate to indicate the type of integer comparison we're performing and alter the costs accordingly. Differential Revision: https://reviews.llvm.org/D57013 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351810 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts commit r351801, as it caused errors on (so far) ppc64be and aarch64 buildbots - the reason is yet unknown. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351811 91177308-0d34-0410-b5e6-96231b3b80d8
Similar to horizontal ops on D56777, the vpermilpd/vpermilps variable mask ops has local forwarding disabled, adding +1cy to the use latency for the result. Differential Revision: https://reviews.llvm.org/D57022 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351815 91177308-0d34-0410-b5e6-96231b3b80d8
…NFCI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351816 91177308-0d34-0410-b5e6-96231b3b80d8
Similar to horizontal ops on D56777, the sse2 (but not mmx) bit shift ops has local forwarding disabled, adding +1cy to the use latency for the result. Differential Revision: https://reviews.llvm.org/D57026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351817 91177308-0d34-0410-b5e6-96231b3b80d8
…,Y)) For constant bit select patterns, replace one AND with a ANDNP, allowing us to reuse the constant mask. Only do this if the mask has multiple uses (to avoid losing load folding) or if we have XOP as its VPCMOV can handle most folding commutations. This also requires computeKnownBitsForTargetNode support for X86ISD::ANDNP and X86ISD::FOR to prevent regressions in fabs/fcopysign patterns. Differential Revision: https://reviews.llvm.org/D55935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351819 91177308-0d34-0410-b5e6-96231b3b80d8
llvm::is_trivially_copyable portability is verified at compile time using std::is_trivially_copyable as the reference implementation. Unfortunately, the latter is not available on all platforms, so introduce a proper configure check to detect if it is available on the target platform. In a similar manner, std::is_copy_assignable is not fully supported for gcc4.9. Provide a portable (?) implementation instead. Differential Revision: https://reviews.llvm.org/D57018 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351820 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351821 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351822 91177308-0d34-0410-b5e6-96231b3b80d8
Previously we had names like 'Call' or 'Tail'. This potentially clashes with the naming scheme used elsewhere in RISCVInstrInfo.td. Many other backends would use names like AArch64call or PPCtail. I prefer the SystemZ approach, which uses prefixed all-lowercase names. This matches the naming scheme used for target-independent SelectionDAG nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351823 91177308-0d34-0410-b5e6-96231b3b80d8
Currently disassembleObject() is a ~550 lines length function. This patch extracts the code that creates a section->their relocation mapping into a new helper function to simplify/reduce it a bit. Differential revision: https://reviews.llvm.org/D57019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351824 91177308-0d34-0410-b5e6-96231b3b80d8
vecbo (insertsubv undef, X, Z), (insertsubv undef, Y, Z) --> insertsubv VecC, (vecbo X, Y), Z This is another step in generic vector narrowing. It's also a step towards more horizontal op formation specifically for x86 (although we still failed to match those in the affected tests). The scalarization cases are also not optimal (we should be scalarizing those), but it's still an improvement to use a narrower vector op when we know part of the result must be constant because both inputs are undef in some vector lanes. I think a similar match but checking for a constant operand might help some of the cases in D51553. Differential Revision: https://reviews.llvm.org/D56875 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351825 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351827 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351828 91177308-0d34-0410-b5e6-96231b3b80d8
These technically should be under a MONITOR cpuid bit, but we tag them as SSE3 so I've done that here as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351829 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351831 91177308-0d34-0410-b5e6-96231b3b80d8
As discovered in D56774 the command line gets to long, so use a response file to give the script the libs. This change has been tested and is confirmed working for me. Commited on behalf of Jakob Bornecrantz Differential Revision: https://reviews.llvm.org/D56781 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351833 91177308-0d34-0410-b5e6-96231b3b80d8
The existing test unintentionally shows that we have prematurely optimized the shuffle into a vector concat and lost the undef info, so it is not affected by a basic improvement to SimplifyDemandedVectorElts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351834 91177308-0d34-0410-b5e6-96231b3b80d8
… rdpmc and rdtsc/rdtscp tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351835 91177308-0d34-0410-b5e6-96231b3b80d8
… tests We're getting pretty close to matching/exceeding test coverage of the test\CodeGen\X86\*-schedule.ll files, which should allow us to get rid of -print-schedule and fix PR37160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351836 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351837 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: A couple of changes in the Scudo documentation: - tag the shell code blocks as `console`; - document error messages that are displayed in some termination conditions, the reason they triggered, and potential causes. Reviewers: eugenis, enh Reviewed By: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56857 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351838 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351840 91177308-0d34-0410-b5e6-96231b3b80d8
Matches test coverage of test\CodeGen\X86\avx512vpopcntdq-schedule.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351842 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: Initial function labels must follow the debug location for the correct relocation info generation. Reviewers: tra, jlebar, echristo Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D45784 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351843 91177308-0d34-0410-b5e6-96231b3b80d8
This is still causing compilation crashes in some targets. Will follow up shortly with a repro. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351845 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: Enable full support for the debug info. Reviewers: echristo Subscribers: jholewinski, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46189 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351846 91177308-0d34-0410-b5e6-96231b3b80d8
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