Original 80186 pin to SystemVerilog "wire" mappings

[r-vvenn]

Hi,

I'm currently working on a project that originally involved an 80186 CPU and I'm hoping to be able to drop this design into it.

While some signals are obvious:

nmi = NMI
irq[0] = INT0
data_m_data_in[15:0] & data_m_data_out[15:0] = AD0-AD15
etc.

... others aren't:

DRQ0/DRQ1
TEST
BHE (is this one half of data_m_bytesel?)

I understand that not everything can be implemented 1:1 on an FPGA, but if you had a signal legend when designing this from the original CPU spec, it would be extremely helpful and save a ton of reverse-engineering effort, even if it was rough and unpolished.

Thanks and much appreciated if possible!

Ryan