[qwen4exp T1] Expert tiering / cache (VRAM <-> RAM <-> SSD) (L, defer) #825

• Scope: only for GPU-addressable memory < model (UD-Q4_K_XL class on this box; dGPU). Design: provider abstraction (vLLM RFC), per-layer LRU/LFU-decay cache with async slot upload and id->slot remap (llama.cpp #27861), per-byte slot sizing (Strata finding 8), optional static warm-start profile (STRP format), --dump-routing tool.
• Acceptance: gated by a measurement first: record routing traces (dotLLM CPU oracle) on 3 workloads and report per-layer LRU-64/128 hit rates and static-profile transfer; build only if > 60% hit at <= 15% of experts. On this box also measure heap-0 vs SSD-mmap fallback for a 111 GB file.
• Deps: V1, M1 (verify windows touch more experts).

Context: Qwen3.8-Flash-Next (arch qwen4_exp, 176B/6B active, 48 layers = 36 GDN + 12 QSA, 512-expert top-10 softmax MoE + shared expert, 4-stream gated residual, n-gram table on layer 1, MTP head). Strata (Niko1221/Strata) is the performance target (measured on this box 2026-10-07: IQ2_XS 50 tok/s decode with MTP, ~450-620 prefill). Reference chain: HF transformers qwen4_exp, llama.cpp -dev none CPU (not Vulkan), KL via llama-perplexity. Epic: see parent.

Parent: #814