Merged master:92063228f85 into amd-gfx:8793c74c592

Local branch amd-gfx 8793c74 Merged master:20c9bb44ec1 into amd-gfx:54bd13cd900
Remote branch master 9206322 [lldb/CMake] Fix typo that prevented regenerating the bindings

lldb/bindings/CMakeLists.txt

@@ -1,4 +1,4 @@
-file(GLOB SWIG_INTERFACES interfaces/*.i)
+file(GLOB SWIG_INTERFACES interface/*.i)
 file(GLOB_RECURSE SWIG_SOURCES *.swig)
 file(GLOB SWIG_HEADERS
   ${LLDB_SOURCE_DIR}/include/lldb/API/*.h

lldb/test/API/functionalities/thread_plan/wrap_step_over.py

@@ -3,14 +3,16 @@
 class WrapStepOver():
     def __init__(self, thread_plan, args_data, dict):
         self.plan = thread_plan
-        frame_0 = thread_plan.GetThread().frames[0]
+        thread = thread_plan.GetThread()
+        target = thread.GetProcess().GetTarget()
+        frame_0 = thread.frames[0]
         line_entry = frame_0.line_entry
         start_addr = line_entry.addr
         end_addr = line_entry.end_addr
-        range_size = int(end_addr) - int(start_addr)
+        range_size = end_addr.GetLoadAddress(target) - start_addr.GetLoadAddress(target)
         error = lldb.SBError()
         self.sub_plan = thread_plan.QueueThreadPlanForStepOverRange(start_addr, range_size)
-        
+
     def should_step(self):
         return False
 

llvm/lib/Target/AArch64/AArch64CallingConvention.td

@@ -384,6 +384,10 @@ def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
                                            D8,  D9,  D10, D11,
                                            D12, D13, D14, D15)>;
 
+// A variant for treating X18 as callee saved, when interfacing with
+// code that needs X18 to be preserved.
+def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>;
+
 // Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
 // and not (LR,FP) pairs.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -2389,6 +2389,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
   const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
       MF.getSubtarget().getRegisterInfo());
+  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   unsigned UnspilledCSGPR = AArch64::NoRegister;
   unsigned UnspilledCSGPRPaired = AArch64::NoRegister;
@@ -2437,6 +2438,16 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
     }
   }
 
+  if (MF.getFunction().getCallingConv() == CallingConv::Win64 &&
+      !Subtarget.isTargetWindows()) {
+    // For Windows calling convention on a non-windows OS, where X18 is treated
+    // as reserved, back up X18 when entering non-windows code (marked with the
+    // Windows calling convention) and restore when returning regardless of
+    // whether the individual function uses it - it might call other functions
+    // that clobber it.
+    SavedRegs.set(AArch64::X18);
+  }
+
   // Calculates the callee saved stack size.
   unsigned CSStackSize = 0;
   unsigned SVECSStackSize = 0;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -3958,6 +3958,13 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization(
   CallingConv::ID CallerCC = CallerF.getCallingConv();
   bool CCMatch = CallerCC == CalleeCC;
 
+  // When using the Windows calling convention on a non-windows OS, we want
+  // to back up and restore X18 in such functions; we can't do a tail call
+  // from those functions.
+  if (CallerCC == CallingConv::Win64 && !Subtarget->isTargetWindows() &&
+      CalleeCC != CallingConv::Win64)
+    return false;
+
   // Byval parameters hand the function a pointer directly into the stack area
   // we want to reuse during a tail call. Working around this *is* possible (see
   // X86) but less efficient and uglier in LowerCall.

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -71,6 +71,10 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     return CSR_AArch64_AAPCS_SwiftError_SaveList;
   if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
     return CSR_AArch64_RT_MostRegs_SaveList;
+  if (MF->getFunction().getCallingConv() == CallingConv::Win64)
+    // This is for OSes other than Windows; Windows is a separate case further
+    // above.
+    return CSR_AArch64_AAPCS_X18_SaveList;
   return CSR_AArch64_AAPCS_SaveList;
 }
 

llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll

@@ -1,18 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 define win64cc void @pass_va(i32 %count, ...) nounwind {
+; CHECK-LABEL: pass_va:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sub sp, sp, #96 // =96
+; CHECK-NEXT:    add x8, sp, #40 // =40
+; CHECK-NEXT:    add x0, sp, #40 // =40
+; CHECK-NEXT:    stp x30, x18, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    stp x1, x2, [sp, #40]
+; CHECK-NEXT:    stp x3, x4, [sp, #56]
+; CHECK-NEXT:    stp x5, x6, [sp, #72]
+; CHECK-NEXT:    str x7, [sp, #88]
+; CHECK-NEXT:    str x8, [sp, #8]
+; CHECK-NEXT:    bl other_func
+; CHECK-NEXT:    ldp x30, x18, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    add sp, sp, #96 // =96
+; CHECK-NEXT:    ret
 entry:
-; CHECK: str     x30, [sp, #-80]!
-; CHECK: add     x8, sp, #24
-; CHECK: add     x0, sp, #24
-; CHECK: stp     x1, x2, [sp, #24]
-; CHECK: stp     x3, x4, [sp, #40]
-; CHECK: stp     x5, x6, [sp, #56]
-; CHECK: str     x7, [sp, #72]
-; CHECK: str     x8, [sp, #8]
-; CHECK: bl      other_func
-; CHECK: ldr     x30, [sp], #80
-; CHECK: ret
   %ap = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap1)
@@ -26,14 +31,15 @@ declare void @other_func(i8*) local_unnamed_addr
 declare void @llvm.va_start(i8*) nounwind
 declare void @llvm.va_copy(i8*, i8*) nounwind
 
-; CHECK-LABEL: f9:
-; CHECK: sub     sp, sp, #16
-; CHECK: add     x8, sp, #24
-; CHECK: add     x0, sp, #24
-; CHECK: str     x8, [sp, #8]
-; CHECK: add     sp, sp, #16
-; CHECK: ret
 define win64cc i8* @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, i64 %a8, ...) nounwind {
+; CHECK-LABEL: f9:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str x18, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    add x8, sp, #24 // =24
+; CHECK-NEXT:    add x0, sp, #24 // =24
+; CHECK-NEXT:    str x8, [sp, #8]
+; CHECK-NEXT:    ldr x18, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
 entry:
   %ap = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*
@@ -42,14 +48,15 @@ entry:
   ret i8* %ap2
 }
 
-; CHECK-LABEL: f8:
-; CHECK: sub     sp, sp, #16
-; CHECK: add     x8, sp, #16
-; CHECK: add     x0, sp, #16
-; CHECK: str     x8, [sp, #8]
-; CHECK: add     sp, sp, #16
-; CHECK: ret
 define win64cc i8* @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, ...) nounwind {
+; CHECK-LABEL: f8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str x18, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    add x8, sp, #16 // =16
+; CHECK-NEXT:    add x0, sp, #16 // =16
+; CHECK-NEXT:    str x8, [sp, #8]
+; CHECK-NEXT:    ldr x18, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
 entry:
   %ap = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*
@@ -58,15 +65,16 @@ entry:
   ret i8* %ap2
 }
 
-; CHECK-LABEL: f7:
-; CHECK: sub     sp, sp, #32
-; CHECK: add     x8, sp, #24
-; CHECK: str     x7, [sp, #24]
-; CHECK: add     x0, sp, #24
-; CHECK: str     x8, [sp, #8]
-; CHECK: add     sp, sp, #32
-; CHECK: ret
 define win64cc i8* @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, ...) nounwind {
+; CHECK-LABEL: f7:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str x18, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-NEXT:    add x8, sp, #24 // =24
+; CHECK-NEXT:    str x7, [sp, #24]
+; CHECK-NEXT:    add x0, sp, #24 // =24
+; CHECK-NEXT:    str x8, [sp, #8]
+; CHECK-NEXT:    ldr x18, [sp], #32 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
 entry:
   %ap = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*

llvm/test/CodeGen/AArch64/win64cc-backup-x18.ll

@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+;; Testing that x18 is backed up and restored, and that x29 (if used) still
+;; points to the x29,x30 pair on the stack.
+
+; RUN: llc < %s -mtriple=aarch64-linux-gnu --frame-pointer=non-leaf | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu --frame-pointer=non-leaf -mattr=+reserve-x18 | FileCheck %s
+
+declare dso_local void @other()
+
+define dso_local win64cc void @func() #0 {
+; CHECK-LABEL: func:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT:    str x18, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT:    mov x29, sp
+; CHECK-NEXT:    bl other
+; CHECK-NEXT:    ldr x18, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT:    ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT:    ret
+entry:
+  tail call void @other()
+  ret void
+}
+
+attributes #0 = { nounwind }

llvm/test/CodeGen/X86/i1narrowfail.ll

@@ -1,8 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
 
-; CHECK-LABEL: @foo
-; CHECK: orb     $16
 define void @foo(i64* %ptr) {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    orb $16, (%rdi)
+; CHECK-NEXT:    retq
   %r11 = load i64, i64* %ptr, align 8
   %r12 = or i64 16, %r11
   store i64 %r12, i64* %ptr, align 8

llvm/test/CodeGen/X86/narrow_op-1.ll

@@ -1,28 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 	%struct.bf = type { i64, i16, i16, i32 }
 @bfi = common global %struct.bf zeroinitializer, align 16
 
 define void @t1() nounwind optsize ssp {
+; CHECK-LABEL: t1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    orb $1, bfi+{{.*}}(%rip)
+; CHECK-NEXT:    retq
 entry:
 	%0 = load i32, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	%1 = or i32 %0, 65536
 	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
 
-; CHECK-LABEL: t1:
-; CHECK: orb $1
-; CHECK-NEXT: ret
 }
 
 define void @t2() nounwind optsize ssp {
+; CHECK-LABEL: t2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    orl $16842752, bfi+{{.*}}(%rip) # imm = 0x1010000
+; CHECK-NEXT:    retq
 entry:
 	%0 = load i32, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	%1 = or i32 %0, 16842752
 	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf, %struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
 
-; CHECK-LABEL: t2:
-; CHECK: orl $16842752
-; CHECK-NEXT: ret
 }