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[RISCV] Optimize multiplication by constant
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... to shift/add or shift/sub.

Do not enable it on riscv32 with the M extension where decomposeMulByConstant
may not be an optimization.

Reviewed By: luismarques, MaskRay

Differential Revision: https://reviews.llvm.org/D82660
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benshi001 authored and MaskRay committed Jul 8, 2020
1 parent 34c4852 commit cb82de2
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Showing 3 changed files with 125 additions and 146 deletions.
21 changes: 21 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"

using namespace llvm;
Expand Down Expand Up @@ -2978,6 +2979,26 @@ bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {
return true;
}

bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
SDValue C) const {
// Check integral scalar types.
if (VT.isScalarInteger()) {
// Do not perform the transformation on riscv32 with the M extension.
if (!Subtarget.is64Bit() && Subtarget.hasStdExtM())
return false;
if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
if (ConstNode->getAPIntValue().getBitWidth() > 8 * sizeof(int64_t))
return false;
int64_t Imm = ConstNode->getSExtValue();
if (isPowerOf2_64(Imm + 1) || isPowerOf2_64(Imm - 1) ||
isPowerOf2_64(1 - Imm) || isPowerOf2_64(-1 - Imm))
return true;
}
}

return false;
}

#define GET_REGISTER_MATCHER
#include "RISCVGenAsmMatcher.inc"

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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -185,6 +185,9 @@ class RISCVTargetLowering : public TargetLowering {
bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
bool shouldConsiderGEPOffsetSplit() const override { return true; }

bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
SDValue C) const override;

TargetLowering::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI,
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