Merge "[AMDGPU] Avoid more hard-coded line numbers in error message c…

…hecks" into amd-gfx
jaebaek · Apr 24, 2020 · ae0e477 · ae0e477
2 parents b801492 + c24f2a4
commit ae0e477
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Showing 2 changed files with 2 additions and 4 deletions.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:27: expected a named register
-# CHECK: scratchWaveOffsetReg:  ''
 ---
 name: empty_scratch_wave_offset_reg
 machineFunctionInfo:
   scratchWaveOffsetReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 

diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:33: incorrect register class for field
-# CHECK: scratchWaveOffsetReg:  '$vgpr0'
 
 ---
 name: wrong_reg_class_scratch_wave_offset_reg
 machineFunctionInfo:
   scratchWaveOffsetReg:  '$vgpr0'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0: