Merged master:710fa2c4ee3 into amd-gfx:ca022c58f8c

Local branch amd-gfx ca022c5 Merged master:9c198b550eb into amd-gfx:319f48f5c47
Remote branch master 710fa2c [lldb] Make module-ownership.mm test more robust against AST node ordering

compiler-rt/test/profile/Inputs/instrprof-gcov-multithread_fork.cpp

@@ -1,27 +1,17 @@
 #include <sys/types.h>
 #include <thread>
 #include <unistd.h>
-#include <vector>
 
 template <typename T>
 void launcher(T func) {
-  std::vector<std::thread> pool;
+  auto t1 = std::thread(func);
+  auto t2 = std::thread(func);
 
-  for (int i = 0; i < 10; i++) {
-    pool.emplace_back(std::thread(func));
-  }
-
-  for (auto &t : pool) {
-    t.join();
-  }
+  t1.join();
+  t2.join();
 }
 
-void h() {}
-
-void g() {
-  fork();
-  launcher<>(h);
-}
+void g() {}
 
 void f() {
   fork();

lldb/test/Shell/SymbolFile/DWARF/module-ownership.mm

@@ -1,6 +1,8 @@
 // RUN: %clang --target=x86_64-apple-macosx -g -gmodules \
 // RUN:    -fmodules -fmodules-cache-path=%t.cache \
 // RUN:    -c -o %t.o %s -I%S/Inputs
+// RUN: lldb-test symbols -dump-clang-ast %t.o | FileCheck --check-prefix CHECK-ANON-S1 %s
+// RUN: lldb-test symbols -dump-clang-ast %t.o | FileCheck --check-prefix CHECK-ANON-S2 %s
 // RUN: lldb-test symbols -dump-clang-ast %t.o | FileCheck %s
 // Verify that the owning module information from DWARF is preserved in the AST.
 
@@ -20,11 +22,11 @@
 // CHECK-TOPLEVELSTRUCT: -FieldDecl {{.*}} in A a 'int'
 
 Struct s2;
-// CHECK-DAG: CXXRecordDecl {{.*}} imported in A struct
+// CHECK-ANON-S1: CXXRecordDecl {{.*}} imported in A struct
 
 StructB s3;
-// CHECK-DAG: CXXRecordDecl {{.*}} imported in A.B struct
-// CHECK-DAG: -FieldDecl {{.*}} in A.B b 'int'
+// CHECK-ANON-S2: CXXRecordDecl {{.*}} imported in A.B struct
+// CHECK-ANON-S2: -FieldDecl {{.*}} in A.B b 'int'
 
 Nested s4;
 // CHECK-DAG: CXXRecordDecl {{.*}} imported in A struct Nested

llvm/include/llvm/Remarks/Remark.h

@@ -14,8 +14,8 @@
 #define LLVM_REMARKS_REMARK_H
 
 #include "llvm-c/Remarks.h"
-#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/CBindingWrapping.h"
 #include <string>

llvm/include/llvm/Remarks/RemarkStringTable.h

@@ -17,18 +17,18 @@
 #define LLVM_REMARKS_REMARK_STRING_TABLE_H
 
 #include "llvm/ADT/StringMap.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/Remarks/Remark.h"
 #include "llvm/Support/Allocator.h"
 #include <vector>
 
 namespace llvm {
 
 class raw_ostream;
+class StringRef;
 
 namespace remarks {
 
 struct ParsedStringTable;
+struct Remark;
 
 /// The string table used for serializing remarks.
 /// This table can be for example serialized in a section to be consumed after

llvm/include/llvm/Support/AArch64TargetParser.h

@@ -15,12 +15,14 @@
 #define LLVM_SUPPORT_AARCH64TARGETPARSERCOMMON_H
 
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/Support/ARMTargetParser.h"
 #include <vector>
 
 // FIXME:This should be made into class design,to avoid dupplication.
 namespace llvm {
+
+class Triple;
+
 namespace AArch64 {
 
 // Arch extension modifiers for CPUs.

llvm/include/llvm/Support/ARMTargetParser.h

@@ -15,11 +15,13 @@
 #define LLVM_SUPPORT_ARMTARGETPARSER_H
 
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Triple.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include <vector>
 
 namespace llvm {
+
+class Triple;
+
 namespace ARM {
 
 // Arch extension modifiers for CPUs.

llvm/lib/Remarks/Remark.cpp

@@ -11,8 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Remarks/Remark.h"
-#include "llvm-c/Remarks.h"
-#include "llvm/Support/CBindingWrapping.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;

llvm/lib/Remarks/RemarkStringTable.cpp

@@ -11,10 +11,10 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Remarks/RemarkStringTable.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/Remarks/Remark.h"
 #include "llvm/Remarks/RemarkParser.h"
-#include "llvm/Support/EndianStream.h"
-#include "llvm/Support/Error.h"
+#include "llvm/Support/raw_ostream.h"
 #include <vector>
 
 using namespace llvm;

llvm/lib/Support/AArch64TargetParser.cpp

@@ -12,8 +12,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/AArch64TargetParser.h"
-#include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
 #include <cctype>
 
 using namespace llvm;

llvm/lib/Support/ARMTargetParser.cpp

@@ -13,6 +13,7 @@
 
 #include "llvm/Support/ARMTargetParser.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
 #include <cctype>
 
 using namespace llvm;

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -35565,7 +35565,8 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
     // broadcast(bitcast(src)) -> bitcast(broadcast(src))
     // 32-bit targets have to bitcast i64 to f64, so better to bitcast upward.
     if (Src.getOpcode() == ISD::BITCAST &&
-        SrcVT.getScalarSizeInBits() == BCVT.getScalarSizeInBits()) {
+        SrcVT.getScalarSizeInBits() == BCVT.getScalarSizeInBits() &&
+        DAG.getTargetLoweringInfo().isTypeLegal(BCVT)) {
       EVT NewVT = EVT::getVectorVT(*DAG.getContext(), BCVT.getScalarType(),
                                    VT.getVectorNumElements());
       return DAG.getBitcast(VT, DAG.getNode(X86ISD::VBROADCAST, DL, NewVT, BC));

llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll

@@ -778,6 +778,32 @@ define <32 x i8> @constant_fold_pshufb_256() {
   ret <32 x i8> %1
 }
 
+define i32 @broadcast_v2i64_multiuse(i64* %p0) {
+; X86-LABEL: broadcast_v2i64_multiuse:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X86-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; X86-NEXT:    vextractps $2, %xmm0, %eax
+; X86-NEXT:    addl (%ecx), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: broadcast_v2i64_multiuse:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movl (%rdi), %eax
+; X64-NEXT:    addl %eax, %eax
+; X64-NEXT:    retq
+entry:
+  %tmp = load i64, i64* %p0, align 8
+  %tmp1 = trunc i64 %tmp to i32
+  %tmp2 = insertelement <2 x i64> undef, i64 %tmp, i32 0
+  %tmp3 = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <2 x i32> zeroinitializer
+  %tmp4 = trunc <2 x i64> %tmp3 to <2 x i32>
+  %tmp5 = extractelement <2 x i32> %tmp4, i32 1
+  %tmp6 = add i32 %tmp1, %tmp5
+  ret i32 %tmp6
+}
+
 define <32 x i8> @PR27320(<8 x i32> %a0) {
 ; CHECK-LABEL: PR27320:
 ; CHECK:       # %bb.0:

mlir/include/mlir/Dialect/StandardOps/IR/Ops.td

@@ -109,6 +109,7 @@ class ArithmeticOp<string mnemonic, list<OpTrait> traits = []> :
 // integer tensor.  The custom assembly form of the operation is as follows
 //
 //     <op>i %0, %1 : i32
+//
 class IntArithmeticOp<string mnemonic, list<OpTrait> traits = []> :
     ArithmeticOp<mnemonic, traits>,
     Arguments<(ins SignlessIntegerLike:$lhs, SignlessIntegerLike:$rhs)>;
@@ -121,10 +122,23 @@ class IntArithmeticOp<string mnemonic, list<OpTrait> traits = []> :
 // is as follows
 //
 //     <op>f %0, %1 : f32
+//
 class FloatArithmeticOp<string mnemonic, list<OpTrait> traits = []> :
     ArithmeticOp<mnemonic, traits>,
     Arguments<(ins FloatLike:$lhs, FloatLike:$rhs)>;
 
+// Base class for standard arithmetic operations on complex numbers with a
+// floating-point element type.
+// These operations take two operands and return one result, all of which must
+// be complex numbers of the same type.
+// The assembly format is as follows
+//
+//     <op>cf %0, %1 : complex<f32>
+//
+class ComplexFloatArithmeticOp<string mnemonic, list<OpTrait> traits = []> :
+    ArithmeticOp<mnemonic, traits>,
+    Arguments<(ins Complex<AnyFloat>:$lhs, Complex<AnyFloat>:$rhs)>;
+
 // Base class for memref allocating ops: alloca and alloc.
 //
 //   %0 = alloclike(%m)[%s] : memref<8x?xf32, (d0, d1)[s0] -> ((d0 + s0), d1)>
@@ -201,6 +215,26 @@ def AbsFOp : FloatUnaryOp<"absf"> {
   }];
 }
 
+//===----------------------------------------------------------------------===//
+// AddCFOp
+//===----------------------------------------------------------------------===//
+
+def AddCFOp : ComplexFloatArithmeticOp<"addcf"> {
+  let summary = "complex number addition";
+  let description = [{
+    The `addcf` operation takes two complex number operands and returns their
+    sum, a single complex number.
+    All operands and result must be of the same type, a complex number with a
+    floating-point element type.
+
+    Example:
+
+    ```mlir
+    %a = addcf %b, %c : complex<f32>
+    ```
+  }];
+}
+
 //===----------------------------------------------------------------------===//
 // AddFOp
 //===----------------------------------------------------------------------===//
@@ -2407,6 +2441,26 @@ def StoreOp : Std_Op<"store",
   }];
 }
 
+//===----------------------------------------------------------------------===//
+// SubCFOp
+//===----------------------------------------------------------------------===//
+
+def SubCFOp : ComplexFloatArithmeticOp<"subcf"> {
+  let summary = "complex number subtraction";
+  let description = [{
+    The `subcf` operation takes two complex number operands and returns their
+    difference, a single complex number.
+    All operands and result must be of the same type, a complex number with a
+    floating-point element type.
+
+    Example:
+
+    ```mlir
+    %a = subcf %b, %c : complex<f32>
+    ```
+  }];
+}
+
 //===----------------------------------------------------------------------===//
 // SubFOp
 //===----------------------------------------------------------------------===//

mlir/include/mlir/IR/OpBase.td

@@ -719,7 +719,6 @@ def SignlessIntegerOrFloatLike : TypeConstraint<Or<[
     SignlessIntegerLike.predicate, FloatLike.predicate]>,
     "signless-integer-like or floating-point-like">;
 
-
 //===----------------------------------------------------------------------===//
 // Attribute definitions
 //===----------------------------------------------------------------------===//