This is the source code of my first pipelined CPU based on RISC-V's architecture. It took a month and a half of work to make this project become real. Many thanks to all of my teachers of the UCM and to the Open Redstone Engineers for giving me the chance of learning everything that I needed to know.
Currently this CPU has:
- Internal Instruction Rom and Program Counter
- Register File
- ALU capable of add/sub, and, xor, or, and shift logical left/right and shift arith right.
- Data Memory (RAM)
- It is pipelined
- No Hazard Unit
- No branching