Support for Bitstream Generation on Versal Platforms

[Mmiglio]

Dear all,

I'm setting up an ipbb-based project targeting a Versal platform.
The Vivado project is generated and implemented correctly. However, when producing the bitstream using ipbb vivado bitfile, I encounter the following error:

bitfile | Command: write_bitstream -force /home/matteomi/feroce-ipbb/proj/testFeroceVersal/testFeroceVersal/testFeroceVersal.runs/impl_1/fpga.bit
bitfile | 0 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
bitfile | write_bitstream failed
bitfile | ERROR: [Common 17-69] Command failed: write_bitstream is not supported for versal parts. Please use write_device_image for versal parts.
bitfile |
[10:22:45] Vivado error/critical warnings detected                                                                                                                                                                                                                                                                         utils.py:250
           ERROR: [Common 17-69] Command failed: write_bitstream is not supported for versal parts. Please use write_device_image for versal parts.                                                                                                                                                                        utils.py:251
                                                                                                                                                                                                                                                                                                                           utils.py:252
Aborted!

As the error suggests, this is due to the fact that Versal devices require write_device_image (which produces a .pdi file, Programmable Device Image) instead of the standard write_bitstream command.
This .pdi file is then used to generate an xsa file, which can be passed to Vitis.

Currently, I'm working around this limitation by using a custom tcl script to generate the bitstream.
Would it be beneficial to support this workflow natively in ipbus for Versal users?

I'm happy to contribute and help implement this feature if you think it's worth including.