dts: arm: r8a77951: add pin-controller node

Pin controller address is the same for all member of the GEN3 SoC Series, but pinmux configuration is SoC specific. This patch defines pinmux configuration for SCIF(UART) and CAN0 module. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
iotbzh · Oct 21, 2021 · 7d17585 · 7d17585
1 parent 65e98ff
commit 7d17585
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diff --git a/dts/arm/renesas/gen3/r8a77951.dtsi b/dts/arm/renesas/gen3/r8a77951.dtsi
@@ -5,3 +5,36 @@
  */
 
 #include <renesas/gen3/rcar_gen3_cr7.dtsi>
+#include <dt-bindings/pinctrl/rcar-pinctrl.h>
+
+&pfc {
+	can0_data_a_tx: can0_data_a_tx {
+		renesas,rcar-pins = < RCAR_PINMUX_IPSR(4,6,8)
+					RCAR_PINMUX_GPSR(1,23,1) >;
+	};
+
+	can0_data_a_rx: can0_data_a_rx {
+		renesas,rcar-pins = < RCAR_PINMUX_IPSR(4,7,8)
+					RCAR_PINMUX_GPSR(1,24,1) >;
+	};
+
+	scif1_data_a_tx: scif1_data_a_tx {
+		renesas,rcar-pins = < RCAR_PINMUX_IPSR(12,4,0)
+					RCAR_PINMUX_GPSR(5,6,1) >;
+	};
+
+	scif1_data_a_rx: scif1_data_a_rx {
+		renesas,rcar-pins = < RCAR_PINMUX_IPSR(12,3,0)
+					RCAR_PINMUX_GPSR(5,5,1) >;
+	};
+
+	scif2_data_a_tx: scif2_data_a_tx {
+		renesas,rcar-pins = < RCAR_PINMUX_IPSR(13,0,0)
+					RCAR_PINMUX_GPSR(5,10,1) >;
+	};
+
+	scif2_data_a_rx: scif2_data_a_rx {
+		renesas,rcar-pins = < RCAR_PINMUX_IPSR(13,1,0)
+					RCAR_PINMUX_GPSR(5,11,1) >;
+	};
+};
diff --git a/dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi b/dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi
@@ -65,6 +65,11 @@
 			label = "gpio6";
 		};
 
+		pfc: pin-controller@e6060000 {
+			compatible = "renesas,rcar-pinmux";
+			reg = <0xe6060000 0x508>;
+		};
+
 		cmt0: timer@e60f0500 {
 			compatible = "renesas,rcar-cmt";
 			interrupt-parent = <&gic>;