driver: serial: renesas: add pinctrl-0 property

Get pin configuration from device tree to set alternate pin function. Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
iotbzh · Oct 21, 2021 · 32bbe15 · 32bbe15
1 parent c0a17c2
commit 32bbe15
Show file tree

Hide file tree

Showing 3 changed files with 29 additions and 13 deletions.
diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts
@@ -68,6 +68,7 @@
 };
 
 &scif1 {
+	pinctrl-0 = <&scif1_data_a_tx &scif1_data_a_rx>;
 	status = "okay";
 };
 

diff --git a/drivers/serial/uart_rcar.c b/drivers/serial/uart_rcar.c
@@ -19,6 +19,8 @@ struct uart_rcar_cfg {
 	const struct device *clock_dev;
 	struct rcar_cpg_clk mod_clk;
 	struct rcar_cpg_clk bus_clk;
+	const struct rcar_pin *pin_list;
+	uint8_t pin_list_size;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	void (*irq_config_func)(const struct device *dev);
 #endif
@@ -271,6 +273,8 @@ static int uart_rcar_init(const struct device *dev)
 	struct uart_rcar_data *data = DEV_UART_DATA(dev);
 	int ret;
 
+	pinmux_rcar_set_pingroup(config->pin_list, config->pin_list_size);
+
 	ret = clock_control_on(config->clock_dev,
 			       (clock_control_subsys_t *)&config->mod_clk);
 	if (ret < 0) {
@@ -528,19 +532,22 @@ static const struct uart_driver_api uart_rcar_driver_api = {
 };
 
 /* Device Instantiation */
-#define UART_RCAR_DECLARE_CFG(n, IRQ_FUNC_INIT)			    \
-	static const struct uart_rcar_cfg uart_rcar_cfg_##n = {	    \
-		.reg_addr = DT_INST_REG_ADDR(n),		    \
-		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
-		.mod_clk.module =				    \
-			DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module),   \
-		.mod_clk.domain =				    \
-			DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain),   \
-		.bus_clk.module =				    \
-			DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module),   \
-		.bus_clk.domain =				    \
-			DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain),   \
-		IRQ_FUNC_INIT					    \
+#define UART_RCAR_DECLARE_CFG(n, IRQ_FUNC_INIT)			     \
+	static const struct rcar_pin pins_scif##n[] = RCAR_DT_INST_PINS(n);  \
+	static const struct uart_rcar_cfg uart_rcar_cfg_##n = {	             \
+		.reg_addr = DT_INST_REG_ADDR(n),		             \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),          \
+		.mod_clk.module =				             \
+			DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module),            \
+		.mod_clk.domain =				             \
+			DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain),            \
+		.bus_clk.module =				             \
+			DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module),            \
+		.bus_clk.domain =				             \
+			DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain),            \
+		.pin_list = pins_scif##n,                                    \
+		.pin_list_size = ARRAY_SIZE(pins_scif##n),	 	     \
+		IRQ_FUNC_INIT					             \
 	}
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN

diff --git a/dts/bindings/serial/renesas,rcar-scif.yaml b/dts/bindings/serial/renesas,rcar-scif.yaml
@@ -13,3 +13,11 @@ properties:
 
     clocks:
       required: true
+
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        GPIO pin configuration for SCIF RX and TX. The phandles are
+        expected to reference pinctrl nodes, e.g.
+          pinctrl-0 = <&scif1_data_a_tx &scif1_data_a_rx>;